Mythic Case Study
Published in September, 2020, updated in February, 2022, by Lauranne Choquin.

What's New in Codasip

05/16/22
Blog
by Rupert Baines
Design for differentiation: architecture licenses in RISC‑V

05/10/22
Press Release
by David Marsden
Codasip appoints SH Lee to deliver RISC-V innovations to Korean OEMs

05/05/22
Blog
by Jamie Broome
Building the highway to automotive innovation

05/03/22
Press Release
by David Marsden
Codasip adopts Siemens’ OneSpin tools for formal verification

05/02/22
Blog
by Keith Graham
Processor architecture optimization is not a barrier for university researchers

04/29/22
Blog
by Philippe Luc
Building a Swiss cheese model approach for processor verification

04/21/22
Press Release
by David Marsden
Codasip appoints Jamie Broome as its Automotive VP

04/08/22
Whitepaper
by Roddy Urquhart
Semiconductor Scaling is Failing

04/06/22
Press Release
by David Marsden
Codasip appoints Japan EDA veteran

04/04/22
Blog
by Philippe Luc
Measuring the complexity of processor bugs to improve testbench quality

03/24/22
Blog
by Roddy Urquhart
Closing the Gap in SoC Open Standards with RISC-V

03/16/22
Blog
by Lauranne Choquin
How Today’s Engineering Students Will Become the Processor Engineers of Tomorrow