Design for differentiation: architecture licenses in RISC‑V

Codasip appoints SH Lee to deliver RISC-V innovations to Korean OEMs

Building the highway to automotive innovation

Codasip adopts Siemens’ OneSpin tools for formal verification

Processor architecture optimization is not a barrier for university researchers

Building a Swiss cheese model approach for processor verification

Codasip appoints Jamie Broome as its Automotive VP

Semiconductor Scaling is Failing

Codasip appoints Japan EDA veteran

Measuring the complexity of processor bugs to improve testbench quality

Closing the Gap in SoC Open Standards with RISC-V

How Today’s Engineering Students Will Become the Processor Engineers of Tomorrow