Effortless DSP extensions design for embedded RISC-V CPUs – Poster

Whitepaper Cover - Effortless DSP extensions design for embedded RISC-V CPUs – Poster

Embedded devices are resource constrained and run many digital signal processing (DSP) algorithms efficiently on these is challenging. Application-specific processors can improve the performance of an embedded system and reduce power consumption, however the design is time- and effort-consuming, as it also requires the development of a custom toolchain that includes a dedicated compiler and other tools such as a debugger and a simulator.

This poster covers the benefits of combining the RISC-V ISA with processor design automation tools based on a C-like architecture description language called CodAL. It demonstrates how to efficiently customize an embedded RISC-V CPU by adding accelerators for some representative DSP algorithms (FFT, FIR & Median filtering, CORDIC) while reducing the design cost and developers’ efforts.

The different DSP-specific customizations have improved the RISC-V CPU performance by at least 15 times and energy consumption by at least 4 times for the execution of these algorithms. The CodAL description of the introduced accelerators requires at least 3 times fewer lines of code than for other hardware description languages. Moreover, the CodAL description further accelerates time-to-market by automatically generating the custom toolchain.

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