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RISC-V as an enabler of heterogeneous compute – Poster

Whitepaper Cover - RISC-V as an enabler of heterogeneous compute – Poster

Zdenek Prikryl, Codasip’s CTO, presented a poster at RISC-V Summit Europe 2023 on RISC-V as an enabler of heterogeneous compute.


With the end of the well-established scaling, and laws, such as Dennard scaling, Amdahl’s law, or even Moore’s law, the wider industry has started looking at possible solutions. One of the solutions that has emerged is heterogeneous compute.

In its essence it solves the problem by having individual computational blocks, i.e., processors, that are specialized/customized for a certain job or workloads. Although this idea is not new and we can see an evidence of it in the past, the design of such processors has been challenging and requires not only deep technology knowledge, but also a significant amount of resources and time.

In this poster, Zdenek presents a novel approach to heterogeneous compute that is based on pre-verified processors that designers can further innovate using supplied EDA tools. The pre-verified processors and their control and data paths are prepared for the heterogeneous compute and therefore the knowledge and resource requirements are reduced to a minimum. The designers focus on what really matters to them instead of reinventing the wheel for the baseline of the processor or its instruction set.

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