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Paper

Compact CORDIC accelerator implementation for embedded RISC-V core – Poster

Whitepaper Cover - Compact CORDIC accelerator implementation for embedded RISC-V core – Poster

Alexey Shchekin and Ettore Giliberti presented a poster at RISC-V Summit Europe 2023 on Compact CORDIC accelerator implementation for embedded RISC-V core.

Summary:

Trigonometric functions are used in many embedded systems applications, such as signal and image processing, control theory, communication systems and robotics. Taking the advantage of RISC-V ISA flexibility and Codasip processor design technologies, we propose a fast and ef icient implementation of the CORDIC algorithm implemented as custom instruction in an embedded RV32IMCB core in order to smoothly compute trigonometric functions.

This customization improves the performance reducing the processing time by 24x, energy consumption by 13.5x at the cost of an additional 4% of silicon area. The CORDIC accelerator was implemented with 210 lines of CodAL code. Such a compact implementation alongside an automatically generated toolchain significantly shortening the time to ASIP market facilitating IP core customizations.

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