Efficient verification of RISC-V processors – Technical paper Applying a Swiss cheese model strategy
Back to technical papers list
For some time, application-specific instruction processors (ASIPs) have been developed for specialized applications. These have required multi-disciplinary teams with sufficient expertise to develop the instruction set, microarchitecture, and software toolchain. Few companies have had the right combination of skills to develop ASIPs so relatively few have been developed.
With the advent of RISC-V the game has changed. It is now easier to design dedicated computational units and a wider community of engineers needs to be involved. While RISC-V has brought benefits to processor designers, it has not helped with verification.
Verifying a RISC-V processor is no different to verifying processors with another ISA. With a broader community involved in developing or modifying RISC-V processors, there needs to be a greater awareness of how to verify processors efficiently. Processor verification, however, is never trivial but requires combining the strengths of multiple verification techniques.
This technical paper considers how to efficiently verify a RISC-V processor using a multi-layered approach known as the Swiss cheese model adapted from the world of avionics.