RISC-V is an open standard that allows an infinite number of implementations. But RISC-V goes beyond that and encourages processor architects to add new instructions to accelerate your algorithms or applications, for example DSP, AI/ML, while keeping the base instruction set stable. The new instructions may help with the performance, code size, power consumption, or differentiation. These new instructions are usually added when you design the processor, so they cannot be changed after tape-out.
In this paper, Codasip and Menta present a new approach that allows you to avoid this restriction It enables your architects to customize processors in the field by using an eFPGA solution, enabling hardware reconfigurability after tapeout. The eFPGA IP is integrated inside the pipeline of a Codasip RISC-V processor.