Unlocking the potential of RISC-V with HW/SW co-design – Poster

Whitepaper Cover - Unlocking the potential of RISC-V with HW/SW co-design – Poster

Roddy Urquhart, Sr. Technical Marketing Director, presented a poster at RISC-V Summit Europe 2023 on unlocking the potential of RISC-V with HW/SW co-design.


The RISC-V architecture was created to cover a wide range of applications. With a good base integer set, optional standard extensions and a defined approach to custom instructions the RISC-V ISA is well equipped to handle an enormous variety of computational tasks. To date, the majority of the R & D effort into RISC-V cores has been focused on essentially replacing well known cores from legacy proprietary architectures.

With semiconductor scaling slowing if not failing, the main way to achieve improved performance efficiently is with architectural innovation. A wide range of specialized applications is well-suited to the RISC-V ISA but require specialized processor cores. To meet ongoing demands a larger number of custom processor cores are needed but there are a limited number of processor design engineers.

This demand can be met by both reducing the design cycle through processor design automation technology and by using existing RISC-V processor cores as a starting point for customization.

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