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A Tale of Two Approaches to High-Performance IoT


June 21, 2017

EXTENSIBLE PROCESSORS VS ACCELERATORS – AND HOW RISC-V CHANGES THE DYNAMIC

If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented by hardware accelerators to offload complex processing from the main cores. This solution should give the best power and performance outcome.

The accelerators are usually implemented as standalone RTL blocks connected to the main processor bus, and are optimized to be very efficient on the data types they work with. So on the surface they appear to be the logical choice to deliver optimal power and performance.

BUT, HOW DID THIS COMMON ARCHITECTURE COME ABOUT, AND IS IT ALWAYS THE BEST APPROACH?

The how it came about is an easy answer – it came about because when you have a fixed processor IP and an ISA that you cannot change, the use of accelerator IP to offload complex data manipulations is the only practical solution. So in a world dominated by ARM and MIPS, the use of hardware accelerators was the only option.

As they say, when all you have is a hammer, everything looks like a nail.

So the next part of the question is “Are accelerators the best solution?”

That is a much more nuanced discussion, and it is highly dependent on the specific application. What we can say is that for many of the cases when accelerators are used, they are sub optimal. In the narrow context of their own operation they save power (and processing time), however at a system level it may lead to greater power and processing time than the alternative.

The reason for this is that if you need flexible pre and/or post processing of data in addition to the primary data manipulation of the accelerator – you will find the application performing many CPU operations and many memory operation, in addition to the operation of the accelerator. The net result is that any advantage of the accelerator is offset by the overhead of pre and post processing.

WHAT DOES THIS HAVE TO DO WITH RISC-V?

Since RISC-V is both an Open and Extensible ISA – it means you can build an implementation that is compliant to the standard and as such able to take advantage of the rich software ecosystem (OS’, Libraries, etc) – while at the same time utilizing application specific processor optimization and extensions. Something that is not possible with a traditional ARM or MIPS processor.

The advantages of extensions rather than accelerators is that the main processor can do the needed data transformations in an highly efficient manner.

This means what would be in an accelerator context the following sequence

  • Processor Data read
  • Processor Data Pre Process
  • Processor Data write
  • Accelerator Init
  • Accelerator Data Read
  • Accelerator Data transform
  • Accelerator Data Write
  • Processor Data Read
  • Processor Data Post Process
  • Processor Data Write

Becomes

  • Processor Data read
  • Processor Data Pre Process
  • Processor Data Transform (via processor extensions)
  • Processor Data Post Process
  • Processor Data Write

The drastic reduction in system traffic reduces overall system complexity and power. This is not a new concept, but the advent of the extensible RISC-V architecture makes it easier than ever to achieve.

SO ARE EXTENSIONS ALWAYS THE ANSWER?

I would love to say yes, but that would put us back into the “everything’s a nail” situation. The reality is that it depends on your data and your application.
Thanks to the extensibility of the Codix-Bk Core (RISC-V compliant)  and the ease of modifying the implementation of RISC-V using Codix Optimizer you can easily decide if the best answer is an accelerator, or processor optimization/extensions. This is not something that has been possible previously. Sure there were extensible processors, but they locked you into a closed and limited ecosystem.

With Codasip and RISC-V you get the best of both worlds.

Karel Masarik

Karel Masařík

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What is RISC-V? Why We Care and Why You Should Too


September 22, 2016

The RISC-V revolution is happening and changing the way we do business in the semiconductor industry. However, there is one big misconception about it: No, RISC-V is not an open-source processor. Let me try and answer the question “What RISC-V?” and tell you why Codasip truly cares about it – and why you should too.

What is RISC-V?

RISC-V is an open specification of an Instruction Set Architecture (ISA). That is, it describes the way in which software talks to an underlying processor – just like the x86 ISA for Intel/AMD processors and the Armv8 ISA for the latest and greatest Arm processors. Unlike those however, the RISC-V ISA is open (we discuss commercial vs. open-source architecture licenses in a separate blog post) so that anyone can build a processor that supports it. We often get two questions: “Is RISC-V a processor?” and “Does RISC-V mean open-source processors?”. Now you know the answer is No.

What’s the big deal about RISC-V vs. Arm or Intel/AMD?

For companies supplying products to customers, lock-in is a wonderful thing. It means that once the vendor has the customer it is very hard for the customer to change to a competitor’s product. The best way to create lock-in is to have good-enough products and a rich ecosystem. That way, once you have the customer, they have invested too much into the implementation and you have them locked-in for a very long time. Any new competitor must have a better product, but also build an equivalent ecosystem. Even then it will be almost impossible for a customer to do an apples-to-apples comparison based on the merits of the solution.

Just like the old saying that no one ever got fired for buying IBM, these days it is accepted that no-one ever gets fired for using Arm processors. There is a dark side to this however. If companies are not able to compete on the merit of their solutions, progress stagnates. Companies invest just enough to keep customers happy – no more, no less.

RISC-V changes this dynamic since a single software ecosystem built on the RISC-V standard supports many different processor vendors, and the processor vendors must now compete on the merit of their product for different applications. Customers don’t need to settle for good-enough, and competition will mean a significant acceleration of innovation in embedded processors. Also, without the need for each new processor startup to build an expensive ecosystem, many new innovative processor companies will appear.

What’s the downside of commercial architecture licenses?

For customers there is none. For processor IP companies, good-enough is no longer enough. Vendors like Codasip will have to ensure we are meeting and exceeding the customer’s needs and supplying the best possible solution, or they can easily move to a new supplier. Some analysts believe RISC-V will lead to commoditization of the processor IP, however, I believe it will lead to specialization and innovation. It will not be a race to the bottom, but rather an opportunity to supply additional value to customers and users.

Is the RISC-V ISA open source?

Thanks to the work of a number of academic institutions – especially UC-Berkley, the original creators of the RISC-V specification – there are a number of free open-source implementations of the RISC-V ISA. These open-source implementations are already allowing various academic and open-source SoC projects to do work that would have been impossible without an open standard. More importantly, however, commercial companies are free to create their own implementation of RISC-V processors. This gives customers an even greater range of options.

How does RISC-V fit with Codasip and application optimized processors?

RISC-V is a layered and extensible ISA which means a processor can implement the minimal instruction set, well-defined extensions, and custom extensions for a given application. As long as the minimal set needed for a given application is implemented, that application will run on any compatible processor.

This removes one of the biggest barriers for application optimized processors, the effort required to develop the ancillary software around the processor. As such, up until now, most ASIPs (Application Specific Instruction-set Processors) have been used in deeply embedded environments where the software environment was limited, and well defined. Having a common software ecosystem means customers will now be free to add application extensions to any processor, being able to take advantage of the significant improvements they provide, without the downside.

“For many systems, the best processor is one tailored for its task”. Check our blog post on How to extend the “unscalable” RISC architectures.

Who maintains the RISC-V standard?

The standard is maintained by RISC-V International, with members (including Codasip) coming from across the industry including software, systems, semiconductor and IP. The focus of member companies is on building a rich ecosystem of hardware and software that will rival or surpass that of companies like Arm.

What is the future of RISC-V?

Unfortunately I don’t have a magic crystal ball, but after many years in the semiconductor industry, what I can say is that I have never before seen so much interest in a new standard, and such a diverse set of companies working together to make it a reality – including processor IP competitors all targeting the same specification.
Is RISC-V the future? I expect that we will see an explosion of innovation and growth, very similar to what happened in the enterprise software space once people were able to build on common open standards.

As they say – A rising tide lifts all boats. It will be an exciting few years!

Karel Masarik

Karel Masařík

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