Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Architectural Exploration

Architectural exploration

Innovation in architecture to bring greater performance

With semiconductor scaling showing its limits, SoC designers are challenged to find ways of meeting the demand for greater computational performance. A key approach is to innovate architecturally and to create more specialized processing units – domain-specific processors and accelerators. 

Specialized processor cores vary significantly depending on their workload. Some may be readily developed by customizing existing RISC-V cores, and sometimes developing a novel architecture such as a specialized DSP, VLIW, or RISC-V may be necessary. In such cases it is necessary to explore the instruction set architecture (ISA) and microarchitecture to find a good design solution.  

Create novel architectures with processor design automation

Codasip solutions give you the ability to describe the processor in a high-level language and use processor design automation to generate the ISS, software toolchain, RTL, and verification environment. 

Our processor design automation toolset, Codasip Studio, has been applied to RISC, DSP, and VLIW designs and is used for developing Codasip’s RISC-V cores. Processors are described using the CodAL architectural language which covers both instruction accurate (IA) and cycle accurate (CA) descriptions. 

Processor optimization with Codasip Studio and CodAL

After defining the appropriate instruction set, developing a core optimized to a specific application requires architecture exploration and microarchitecture definition.

Exploring the instruction set

Defining the microarchitecture

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