How do you meet the demand for greater computational performance when semiconductor scaling is showing its limits? You innovate architecturally and create more specialized processing units. You customize your compute.
Application specific cores vary significantly depending on their workload. You can develop one by customizing an existing core or you can develop a novel architecture. In any case, you need to explore the Instruction Set Architecture and the microarchitecture to find the right design solution.
Create a novel architecture with design automation
With custom compute solutions, you describe your processor in a high-level language and use design automation to generate the ISS, software toolchain, RTL, and verification environment.
Codasip Studio works with RISC, DSP, and VLIW designs and is used for developing all Codasip RISC-V cores.
The CodAL architectural language description of the core covers both instruction accurate (IA) and cycle accurate (CA) models.
Optimize an existing RISC-V core with Codasip Studio and CodAL
After you have defined the appropriate instruction set, you can explore the architecture and define the microarchitecture for the development of your optimized core.