Highlights from 2022, a turning year for Codasip
January 25, 2023
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January 25, 2023
The start of a new year is a perfect time to look back and reflect on the previous year and our company’s position. At the RISC-V Summit at the end of 2021, our CEO Ron Black said that Scaling is Failing, with regard to Moore’s Law, Dennard Scaling, and Amdahl’s Law, and the industry needs to adjust. Semiconductors are becoming more expensive to build but are no longer returning the expected and required performance improvements; the semiconductor industry needs to reinvent itself. That is not a trivial task, but Codasip has the technology and team needed to drive this change. 2022 was a year when we took our unique custom compute offering to the next level
During the last year, our headcount has grown by about 75 percent. That is a substantial addition of expertise and resource, all joining forces to take on conventional chip design. Some of these new people are senior hires with specific expertise in high-growth areas such as automotive, functional safety, and AI. One reason we attract out-of-the-box thinkers is that we like to do things differently. As a company, we are championing distributed thinking around the future of chip design, and we are working as a team of distributed talent to deliver it. We do have offices in places such as Munich, Barcelona, Cambridge (UK), and most recently Greece, but more than anything I like to see us as an international collective of freethinking individuals working towards a shared goal of disrupting an industry that needs to start doing things differently.
When it comes to finding the absolute best talent, we are believers in both organic and inorganic growth. In 2022, we initiated discussions with an amazing security company in the UK called Cerberus. This highly knowledgeable team really embraced the Codasip philosophy, and we ended up acquiring the company. This was an important piece of the puzzle for us to meet the growing needs for flexibility and customization in secure processors and secure processing, and the team has already taken a very active role in enabling us to win new business. In 2023, we will start seeing the next level of deliverables from the security team together with our functional safety team. We believe a holistic view of safety and security will be incredibly important, especially for the automotive industry, and we are accelerating our efforts to offer an integrated approach that can provide a complimentary safety and security solution that is scalable in either direction.
With the world now opening up after the pandemic, we have had the pleasure of meeting our peers and customers again at key industry events including DAC in the US, ICCAD in China, and Embedded World in Germany, where we were proud to see our low-power L31 core win a Best in Show Award. This customizable RISC-V core is and will continue to unlock innovation in the embedded space, for example within image processing, smart sensors and IoT devices.
The success of RISC-V is and always will be a joint effort, and it is only by being an active and prominent member of the ecosystem that we fully enable our existing and future customers to create uniquely better products. In 2022, we signed up as members of the OpenHW Group, which raised some eyebrows. Why would a commercial core vendor join an organization that provides open-source free cores? Well, in the strong and growing RISC-V community, everyone supporting the open standard benefits us all. We see the roles of open-source IP and commercial IP as complementary and though we sell our cores, we also acknowledge the value of open source as a critical part of the ecosystem and for the success of RISC-V. We also share a strong belief in commercial-grade verification with the OpenHW Group. Codasip is heavily committed to processor verification as a fundamental part of designing processor cores and we are pushing for the establishment of agreed strategies and standards to ensure the quality of RISC-V cores continues to improve.
Of course, we took part in the RISC-V Summit in California in December, where we presented SecuRISC5, a new security initiative, and gave demos of a RISC-V dual-lock step implementation along with performance benefits enabled by our solutions for custom compute.
We are at the start of a disruption in the semiconductor industry and my prediction is that this will accelerate in 2023. Codasip will be at the heart of that disruption. The recent evolution of RISC-V is driven by a strong need for an open ISA alternative with trustworthy ecosystem support. We are establishing new partnerships aligned with our focus on helping the ecosystem increase the adoption and the quality of RISC-V processor IP. Our University Program, launched in 2022, is off to a great start and continues to expand. We look to be at 24 universities by the end of this year, and through our new innovation hub Codasip Labs, we will continue to innovate together with universities, research institutes, and strategic partners in order to identify and build technologies that extend the possibilities of custom compute.
Just a year ago, I called Codasip a well-kept secret. Well, the cat is out of the bag. By now, we notice everyone in the industry knows about Codasip. The future of RISC-V is looking extremely bright, and more is to come from Codasip, rest assured. Make sure to follow us in 2023 and beyond!
May 16, 2022
I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp.
In a traditional processor IP model, there is a clear distinction between an off-the-shelf IP license that gives some level of configuration but no customization, and a fairly expensive architecture license enabling a licensee to use the instruction set with their own custom microarchitecture.
With RISC-V, the complication comes from the fact that it is often described as “an open-source architecture”, so people believe that some source code is licensed. But actually that is not the case at all.
In a traditional model, things are quite straight forward. A standard license for Arm or MIPS lets the customer use an RTL design but not change it at all (aside from a few configuration options perhaps).
Meanwhile, for customers willing to spend a lot of money, an architecture license gives them the right to modify how a processor executes instructions (the issue width, the cache size, etc.). However, it does not generally give the right to modify the instructions (with some exceptions such as the Cortex-M33 that supports Arm Custom Instructions, allowing the implementation of bespoke data processing operations, or Cadence Tensilica).
In an open-source model such as RISC-V, things are somewhat different
The RISC-V architecture is usually described as “open-source”, which implies everyone can use it at no cost.
However, a better description of RISC-V is that it is an “open architecture” or “open standard”. In that sense RISC-V is like C, Wi-Fi or LTE with RISC-V International performing the role of (respectively) ANSI, IEEE 802.11 and 3GPP in defining and managing standards that people are free to implement as they choose. But that is a written standard – not an implementation or a microarchitecture.
Just as is the case with those other open standards, RISC-V licenses can either be open-source or commercial.
You can download open-source designs and have complete freedom to modify them however you wish. Boom, PULP, SweRV and other open-source designs give absolute freedom. But that comes with a cost: they are not supported, the verification is often troublesome, and they may not be of sufficient quality to use in a commercial design. Some companies do use them accepting those compromises; others are understandably wary.
Or you can buy a commercial RISC-V design. There are many companies offering high quality cores delivered as RTL with warranty and full product support. These can be an excellent solution for many customers. Then we are back to something similar to the traditional model: a sort of black box design – although based on an open-standard ISA – in that it cannot be modified or customized to address specific needs. But for many purposes that generic product will be a good fit.
Codasip, as a RISC-V core vendor, does a lot of business on this basis: customers buy a standard RISC-V processor core delivered as RTL and SDK, with high performance, “best-in-class” verification and full support. That is without any architecture license fees, to use it as it is, off the shelf.
But Codasip offers another option. This is an architecture license – and more – delivered as a source code in the CodAL processor description language.
Many of our customers buy a standard Codasip processor IP product delivered as CodAL source and then use Codasip Studio™ which enables them to modify it freely. We provide the flexibility to modify both the microarchitecture and the ISA, precisely what one needs to Design for Differentiation. Customization at ISA level brings higher performance and optimization. What is more, the power and elegance of the Codasip Studio toolset makes this very easy.
This is different to, for example, an Arm architecture license in three ways:
Arm, even with an architecture license, constrains what you are allowed to do. Codasip does not: it is your core and you have control.
Arm cores are developed internally, in traditional ways and not designed to be easy to modify. In contrast, all of Codasip’s cores are developed using Studio and are designed expressly to make customization (both ISA and microarchitecture) straightforward and efficient. That includes automatically creating the software toolchain (customized compiler etc) and verification.
Traditionally the limitation of architecture licenses has been both the cash cost of the license and the engineering resources (cost) required to take advantage of it. Codasip and Studio now make that far easier and hence more affordable with a complete end-to-end architecture customization solution. This dramatically changes the cost equation both of the architecture license fee and the engineering resources required.
Codasip offers the best of both worlds: a portfolio of high-quality standard cores that are a good fit for standard applications, with full verification and support. Or you can upgrade to a cost-effective architecture license, and benefit from custom compute: Architecture optimization, hardware/software co-design, and domain-specific acceleration. Doing so, enables you to freely customize the core in an easy-to-use environment and have a unique product for your unique needs.
February 18, 2022
A couple of years ago, Erik McClure (a Microsoft software developer, at the time) published a blog entitled, RISC Is Fundamentally Unscalable.
This blog was really quite interesting and made some very good points about the limitations of a pure RISC design.
It takes me back: some of my first marketing tasks were around the religious war between RISC & CISC.
However, to a degree, I think Erik’s blog overstates things: nobody today really thinks of RISC-V as being just RISC.
That religious war is long-gone: we have all read Hennessy & Patterson, we all know to use quantitative technique and metrics to analyze performance and to make the inevitable trade-offs. Complex instructions, deeper pipelines, faster/cleaner architectures, power versus area versus performance – those are solved by modelling & data not simplistic binary divides or theological purity.
A key principle of RISC-V from its inception was the ability to add instructions, and there are a number of defined extensions, as optional modules.
There certainly are products using standard RISC-V cores with the standard base ISA. But there are many products with extensions. And for many applications you can do even better.
This ties in very well with the Codasip philosophy: the use of RISC-V as a basic architecture for the benefits of interoperability ecosystem partners and ready-made software. But then add custom instructions for exactly the situation that you need.
Chips are designed for a purpose – processors are used for an application. In some cases, yes, that is a general-purpose processor, and it must cope with all manner of weirdness and generic, unpredictable code. In which case yes, it’s entirely possible the instruction set will grow and grow as we can see in X86 or Arm. This is one reason the RISC-V International organization is proposing profiles with the most common configurations and extensions.
However, in many applications the system is used for a particular purpose running a particular codebase. In that case there’s absolutely no need for the instruction set to become huge: it can be RISC as always intended with a small instruction set, small die area with no overhead and just a few custom instructions for those few very performance-sensitive, critical purposes.
That gives the best of all worlds: high-performance, a small, optimized architecture, industry compatibility, software ecosystem, and yet both area-efficient and power-efficient because there is no need for all the custom logic adding complexity for things that are not required in that application.
There is always a need for basic commonality and interoperability to avoid fragmentation, to get the benefits of the RISC-V ecosystem. But for many systems the best processor is one tailored for its task. RISC-V enables that flexibility and Codasip delivers it.
December 17, 2021
We weren’t sure what to expect from our first major attendance at a #RISCVSummit. Although we were a founding member of RISC-V – as we’ve been saying quite a lot recently – we have been hiding our light under a bushel.
We’ve certainly been busy though – enabling over 2 billion RISC-V cores with our RISC-V processor IP and Studio tools while helping customers use architecture licenses, customization and domain specific compute – but perhaps we neglected the publicity.
However, we are now growing seriously and we know we can’t rest on our laurels. So off to San Francisco we trotted…A magnificent team of seven Codasippers were at the Summit, including a raft of our senior execs: new CEO Ron Black, CRO Brett Cline and CTO Zdeněk Přikryl together with a US sales team and more. Mustn’t forget myself: CMO Rupert Baines!
With Omicron timed to spoil the party, the event’s attendance was never going to be the best ever. A lot of visitors sadly did have to cancel. But while numbers were down, there were still a lot of good meetings and great presentations. Interestingly, the Summit was busier than DAC with which it was co-hosted. DAC is of course a fundamentally important event in the design calendar, but it was clear that RISC-V still brings with it a sense of something new and exciting: a growth opportunity. And who doesn’t love a growth opportunity.
For those of us from outside USA it was also a great opportunity to meet customers face-to-face even if they were not at the event. Doing business over Zoom has been efficient but there is something magic that happens with a CTO, a whiteboard and an engaged customer architect.
Meanwhile, Filip enjoyed his first US trip and clocked up his tourist points.
Ron’s presentation on the end of scaling and need for heterogenous compute was particularly well-received – with plenty of nodding heads in the audience. Watch the video recording of ‘Scaling is Failing’ keynote address here. Ron recently put his thoughts into a blog
The Summit saw some new entrants into the RISC-V ring. It is great to see the growing interest in RISC-V – although you could say they’re late to a party that’s now well and truly underway! We know from our own experience that there are no shortcuts to catch-up.
There were also new launches from existing RISC-V vendors, but from our perspective nothing that changes our outlook nor our prospects on selling our next 2 billion cores.
Our friends at Imperas were making a very good point on the need for better verification in RISC-V – something we passionately believe in (and it was incredible how some people seem not to appreciate). Watch the Imperas RISC-V verification presentation here.
The fact is, the RISC-V market is ripe for domain specific designs, as Ron made clear from his presentation: Dennard, Moore’s, Amdahl’s,..these traditionally immutable laws of semiconductor design and scaling are, well, mutable!
If you missed the event, watch the presentation from Ron Black, Zdeněk’s 10 minute overview to custom instructions in RISC-V and contact us directly to find out how we can help you design the best possible processors to differentiate your product in an increasingly competitive marketplace.
September 13, 2021
Eighteen months ago, I said: “The rise of RISC-V offers us a tremendous platform for innovation and collaboration: it has the potential to change the business model of the entire industry.” I stand by that and indeed am demonstrating my conviction by joining the ranks of a company that’s not only changing the industry business model, but is significantly innovating in RISC-V.
Having taken UltraSoC to its exit (sold to Siemens in June 2020), I was on the lookout for the next opportunity. It didn’t take research to know I wanted to be part of RISC-V. And Codasip has an incredibly strong team I know and respect – having worked with them, via our partnership at UltraSoC, or having known through previous roles in the industry. I jumped at the opportunity to work with a European company in such a strong market position.
Codasip is like other RISC-V IP vendors in that we have a portfolio of standard cores for those who want a standard product. But we have something unique: the custom capabilities of Codasip Studio that take the open-market opportunities of RISC-V to a new level. This radically simplifies the task of differentiation and offering our customers the ability to embed unique features. This creates a virtual bridge for those companies who want the ecosystem of a standard ISA, but also want the flexibility of a custom-designed processor.
The industry momentum and interest in RISC-V continues to grow, unabated… in fact, with even more impetus. Why is this? Well, as I’ve long since preached (I’m told I preach!) since its inception, RISC-V has represented a fundamental shift in the industry – a shift in processor architecture that is only just starting.
Arm has transformed the industry and still (rightly) has a significant following for its architecture. But no-one can deny there are questions over where the company is heading and concern over the implications and longer-term design choices. That is opening up the market to the benefit of SoC designers and the industry as a whole – and, of course, to the benefit of alternative solutions like Codasip.
This is a timely opportunity for RISC-V. And Codasip, with its Studio platform, finds itself at the sweet spot: offering customers all the benefits of the open-standard RISC-V ecosystem combined with the ability to customize and differentiate their designs. This is the best of both worlds – offering a unique value to a significant portion of the market.
Codasip’s proposition means it already has excellent customer traction – it was one of the first companies to commercialize RISC-V IP – but the fact it remains (mostly) a well-kept secret is, from my point of view, a marketing dream come true and a challenge I relish!