Let’s meet at the RISC-V Summit North America 2024 Santa Clara, California! We are exhibiting at this key industry event on 22-23 October. Visit our booth, talk to our team, watch our demos, and get started with your RISC-V and Custom Compute journey!
Software Engineers Are Tomorrow’s Processor Engineers – Keith Graham
Wednesday October 23, 2024 11:30am – 11:48am PDT
RISC-V’s open standard provides a great opportunity to democratize the Domain Specific Processor market. Over the last twenty to thirty years, the processor market was dominated by general purpose closed-architectures. This environment limited processor engineering companies and job prospects. RISC-V enables a new going to market strategy that is not linked to a limited number of processor vendors, but a market strategy where the application and processor integrator defines and develops the Domain Specific Processor, the traditional System-On-Chip (SoC) developer. To extend custom processing to the larger segment of SoC developers, new processor engineers are required. Due to the lack of previous job prospects, there is a processor engineering shortage to sustain the pace of innovation. The RISC-V ecosystem is coming to the rescue. By developing processor Bounded Customization models where the Software Engineer uses standard software programming practices to architect and to develop custom processors, the inadequate supply of processor engineers can be solved. Who better than the application and algorithm engineer to become tomorrow’s processor engineer.
Hardening Linux and FreeBSD on RISC-V with CHERI – Carl Shaw
Wednesday October 23, 2024 2:15pm – 2:33pm PDT
CHERI is an emerging security technology, jointly developed over the last decade by the University of Cambridge and SRI International. In this talk, we will describe the work being done to bring CHERI support to FreeBSD and Linux on RISC-V, where we can provide both memory safety as well as isolating software components to improve run-time safety, security and robustness.
Demo: Securely booting CHERI on a full OS to prevent buffer overflow attacks – Carl Shaw
Date and Time TBA
CHERI is a fine-grained memory protection technology that protects your system against buffer overflows and other memory safety issues. CHERI is implemented in hardware and enabled by supporting software. This demo simulates a real buffer overflow attack on an application running a full OS. We will show how a Codasip application core with CHERI enabled can identify the attack and stop the system without any secrets being accessed.
Poster: Commercializing CHERI on a Codasip A730 RISC-V Application Core – Tariq Kurd
Date TBA
Book a meeting with our team
Our team onsite will be available for private meetings. You can already book some time with us: just let us know when you would be available and what you would like to discuss. We will get back to you with your meeting information. Simply fill out the form below.