Visit Codasip’s presentations at RISC-V Summit North America 2025 on October 21-23.
Learn more about how we make RISC-V customization efficient!
Join our CTO’s presentation
Join this presentation to discover how heterogeneous computing and RISC-V enable efficient handling of modern workloads. This presentation also explains Bounded Customization methodology—a streamlined approach to processor design that focuses on verifying only new instructions, eliminating the need for full re-verification.
Find out more.
Customize after tape-out with Menta and Codasip
Explore how RISC-V’s extensibility enables powerful processor customization—both during development and in-field. This talk presents a flexible approach combining Codasip’s RISC-V processors, automated EDA tools, and Menta’s e-FPGA technology to support evolving workloads and late-stage instruction updates.
Find out more.
Don’t miss your chance to learn more about CHERI
Member day session topic: CHERI 101 and Standardization Session
Presentation by Tariq Kurd, Lead IP Architect, Codasip and Helena Handschuh, SCI Semiconductors
This talk explains the memory safety problem which modern computing systems have, which malicious actors take advantage of so regularly, for example, with ransomware attacks widespread and on the increase.
Find out more.