RISC-V Summit 2021

The RISC-V event of the year is approaching and Codasip is a proud Platinum Sponsor. See what we have in stock for you and meet us there!
Do you want to be a RISC-V leader, not a follower?

Then Design for Differentiation!

RISC-V offers the opportunity for new companies to disrupt the industry. Codasip’s customized solutions open up the potential for your creativity: Design For Differentiation with Codasip Studio and RISC-V cores. Codasip has already shipped an estimated 2bn cores.

Find out how your designs could benefit, see us at RISC-V Summit 2021!


Our Talks

Hosted by DAC, booth #1346

Extending RISC-V Cores in the Field
Zdeněk Přikryl, Codasip & Imen Baili, Menta

Monday, December 6
1-2 pm

Tuesday, December 7
2-3 pm

Wednesday, December 8
3-4 pm

See a map


Scaling is Failing

Ron Black, CEO, Codasip

Wednesday, December 8
2:15–2:25 pm

See on agenda


10 Minute RISC-V Custom Instructions

Zdeněk Přikryl, CTO, Codasip

Monday, December 6
3:05–3:15 pm

See on agenda

Booth Demo

Codasip Application Processor Evaluation Platform
Forrest Pickett, FAE, Codasip

The demo shows a linux prompt and the ability to control a simple LCD screen on the FPGA board.

Booth Demo

Codasip Embedded Processor Evaluation Platform
Forrest Pickett, FAE, Codasip

The demo shows GPIO blinking lights, QSPI being written, I2C measuring the temperature, and two benchmarks running.

Lightning Talk

Using and Extending RISC-V in an Analog Matrix Processor for Neural Networks
David Luo, Mythic & Zdeněk Přikryl, Codasip

Monday, December 6
4:15–4:25 pm

See on agenda

Hosted by DAC

Updating RISC‑V microarchitecture in the field through Menta co‑extended cores and Codasip Studio
Imen Baili, Menta & Zdeněk Přikryl, Codasip

Monday, December 6
5:00–6:00 pm

See on agenda

Our Booth


Find us at booth B10 in the Platinum Sponsor section in the Moscone West Hall.
ℹ️ How to get there

Please note that RISC-V Summit 2021 is co-located with 58th DAC.
ℹ️ Official announcement


This whitepaper by Codasip CTO Zdeněk Přikryl elaborates on the advantages of customized ‘domain specific’ processors using RISC-V. Get the insight!
Get the whitepaper


Codasip Chairman Ron Black will present his keynote on why traditional semiconductor scaling is failing on Wednesday 8th December. In light of this ‘scaling’ challenge facing the industry, Sr. Marketing Director Roddy Urquhart explains the benefits of domain specific accelerators in this video presentation.


Codasip RISC-V Processors are pre-verified processor cores that can be deployed instantly, or easily customized with Codasip Studio to add your secret domain-specific sauce. Check out the selection of low-power, high-performance or advanced application cores for any design needs!
Codasip Studio is a complete EDA toolset for highly automated, easy-to-do customization. The cutting-edge technology walks you through the design path and ensures unbeatably fast and reliable results. Why put up with a generic core when you can have a unique one to match your application?

Meet us there!

    Request a meeting with us at the RISC-V Summit 2021 by filling in the form below. We will make sure to get in touch shortly!

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