Our EDA toolset offers unparalelled level of automation and a market-unique approach to processor design and customization.
The Patented Technology
The technology behind our flagship product, Codasip Studio, employs a revolutionary, patent-protected approach.
In a nutshell, we use one single high-level description of the processor and we replace the manual tasks of writing the RTL, adding custom instructions, updating the compiler etc. with a fully automated workflow. Read on for more info!
Unique Design Method
How others do it
How we do it
The CodAL Language
First of all, we describe the architecture of a RISC-V processor in the CodAL language. CodAL is a high-level hardware description programming language, developed by Codasip specifically for processor architecture description and modelling.
CodAL is based on C, so it is familiar to developers and easy to work with. Even without the expertise to program on the RTL level, it is possible to modify a RISC-V core described in CodAL and get a reliable result.
The CodAL language:
Automated Generation of Customized Tools
- Hardware development kit (HDK) = set of tools necessary to simulate, debug, and successfully integrate the processor RTL into a SoC
- Software development kit (SDK) = set of tools necessary to create, simulate, and debug programs for the newly designed processor
The high-level CodAL model can easily reflect any desired custom changes to the processor design. It is especially convenient in the case of RISC-V, an architecture that is flexible and customizable by its very design – allowing to add a standard instruction set of your choice, or design a custom one while maintaining compliance with the RISC-V standard.
The CodAL model is used by Codasip Studio to generate the complete customized HDK and SDK.
Off-the-shelf Codasip RISC-V Processors are pre-verified, but a new or customized processor core requires new verification. Codasip Studio generates a full UVM environment ready for verification. The generated simulator serves as a golden Reference Model, the generated RTL running in a RTL simulator servers as design-under-test (DUT), and the UVM-based verification process verifies that their behavior is equivalent.