Codasip Extends SweRV Support Package to Include Western Digital SweRV EH2 & EL2 RISC-V Cores

June 2, 2020 News & Docs, Press Releases

Codasip announces the availability of support to the two new SweRV cores, EH1 and EH2. Both are now available, along with all necessary tools and workflows, within Codasip’s exclusive SweRV Support Package.

Codasip releases Support Package for Western Digital’s first RISC-V SweRV Core

April 23, 2020 News & Docs, Press Releases

Codasip announces the official release of its exclusive SweRV Support Package – a comprehensive service for users of SweRV, the new RISC-V superscalar core developed by Western Digital and available free of charge within the CHIPS Alliance repository.

Codasip Awarded European Union Horizon 2020 Funding for Developing New RISC-V Processors

March 18, 2020 News & Docs, Press Releases

Codasip announces that it has received a Horizon 2020 award from the European Union. The award is aimed at developing processor cores for the rapidly growing market for integrated circuits for Internet of Things (IoT), connected cars, drones, and artificial intelligence.