Below you'll find a list of all posts that have been tagged as “2020”
Everybody is familiar with commercial licensing from traditional processor IP vendors. In discussing RISC-V, there is widespread confusion of terminology with RISC-V often being described as “open source”, often understood as “free”. But what is reality?
The area of any part of a design contributes both to the silicon cost and to the power consumption, but a simplistic following of the “A” in a processor IP vendor’s PPA numbers can be misleading. What do you need to know?
Codasip announces that NeuLinker, a high-profile Beijing-based company focused on cutting-edge custom computing technologies, has selected Codasip’s Bk5 RISC-V-based core and the Codasip Studio customization toolset for their AI and security-powering solutions.
Codasip announces opening a new strategic design center in France, which is going to play an important role in the company’s innovation and development plans.
For each embedded product, software developers need to consider whether they need an operating system; and if so, what type of an OS. Operating systems vary considerably and the choice of one for your processor core has important implications. Let us explore them.
The RISC-V ISA is designed in a modular way, meaning that the ISA has several groups of instructions (ISA extensions) that can be enabled or disabled as needed. This allows implementing precisely the instruction groups that the domain needs, without having to pay for area or power that will not be used.
Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance.
Looking at any processor IP, you will find that their vendors emphasise PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider performance.
Codasip and Metrics Design Automation jointly announce the integration of the Metrics SystemVerilog RTL Simulation Platform within Codasip’s Pro SweRV Core™ Support Package.
Codasip announces the official release of Bk7, the most advanced core in the Codasip family of RISC-V processor IP to date, built specifically with customization and domain-specific optimization in mind.
