RISC-V Summit 2021
December 17, 2021
December 17, 2021
We weren’t sure what to expect from our first major attendance at a #RISCVSummit. Although we were a founding member of RISC-V – as we’ve been saying quite a lot recently – we have been hiding our light under a bushel.
We’ve certainly been busy though – enabling over 2 billion RISC-V cores with our RISC-V processor IP and Studio tools while helping customers use architecture licenses, customization and domain specific compute – but perhaps we neglected the publicity.
However, we are now growing seriously and we know we can’t rest on our laurels. So off to San Francisco we trotted…A magnificent team of seven Codasippers were at the Summit, including a raft of our senior execs: new CEO Ron Black, CRO Brett Cline and CTO Zdeněk Přikryl together with a US sales team and more. Mustn’t forget myself: CMO Rupert Baines!
With Omicron timed to spoil the party, the event’s attendance was never going to be the best ever. A lot of visitors sadly did have to cancel. But while numbers were down, there were still a lot of good meetings and great presentations. Interestingly, the Summit was busier than DAC with which it was co-hosted. DAC is of course a fundamentally important event in the design calendar, but it was clear that RISC-V still brings with it a sense of something new and exciting: a growth opportunity. And who doesn’t love a growth opportunity.
For those of us from outside USA it was also a great opportunity to meet customers face-to-face even if they were not at the event. Doing business over Zoom has been efficient but there is something magic that happens with a CTO, a whiteboard and an engaged customer architect.
Meanwhile, Filip enjoyed his first US trip and clocked up his tourist points.
Ron’s presentation on the end of scaling and need for heterogenous compute was particularly well-received – with plenty of nodding heads in the audience. Watch the video recording of ‘Scaling is Failing’ keynote address here. Ron recently put his thoughts into a blog
The Summit saw some new entrants into the RISC-V ring. It is great to see the growing interest in RISC-V – although you could say they’re late to a party that’s now well and truly underway! We know from our own experience that there are no shortcuts to catch-up.
There were also new launches from existing RISC-V vendors, but from our perspective nothing that changes our outlook nor our prospects on selling our next 2 billion cores.
Our friends at Imperas were making a very good point on the need for better verification in RISC-V – something we passionately believe in (and it was incredible how some people seem not to appreciate). Watch the Imperas RISC-V verification presentation here.
The fact is, the RISC-V market is ripe for domain specific designs, as Ron made clear from his presentation: Dennard, Moore’s, Amdahl’s,..these traditionally immutable laws of semiconductor design and scaling are, well, mutable!
If you missed the event, watch the presentation from Ron Black, Zdeněk’s 10 minute overview to custom instructions in RISC-V and contact us directly to find out how we can help you design the best possible processors to differentiate your product in an increasingly competitive marketplace.
September 13, 2021
Eighteen months ago, I said: “The rise of RISC-V offers us a tremendous platform for innovation and collaboration: it has the potential to change the business model of the entire industry.” I stand by that and indeed am demonstrating my conviction by joining the ranks of a company that’s not only changing the industry business model, but is significantly innovating in RISC-V.
Having taken UltraSoC to its exit (sold to Siemens in June 2020), I was on the lookout for the next opportunity. It didn’t take research to know I wanted to be part of RISC-V. And Codasip has an incredibly strong team I know and respect – having worked with them, via our partnership at UltraSoC, or having known through previous roles in the industry. I jumped at the opportunity to work with a European company in such a strong market position.
Codasip is like other RISC-V IP vendors in that we have a portfolio of standard cores for those who want a standard product. But we have something unique: the custom capabilities of Codasip Studio that take the open-market opportunities of RISC-V to a new level. This radically simplifies the task of differentiation and offering our customers the ability to embed unique features. This creates a virtual bridge for those companies who want the ecosystem of a standard ISA, but also want the flexibility of a custom-designed processor.
The industry momentum and interest in RISC-V continues to grow, unabated… in fact, with even more impetus. Why is this? Well, as I’ve long since preached (I’m told I preach!) since its inception, RISC-V has represented a fundamental shift in the industry – a shift in processor architecture that is only just starting.
Arm has transformed the industry and still (rightly) has a significant following for its architecture. But no-one can deny there are questions over where the company is heading and concern over the implications and longer-term design choices. That is opening up the market to the benefit of SoC designers and the industry as a whole – and, of course, to the benefit of alternative solutions like Codasip.
This is a timely opportunity for RISC-V. And Codasip, with its Studio platform, finds itself at the sweet spot: offering customers all the benefits of the open-standard RISC-V ecosystem combined with the ability to customize and differentiate their designs. This is the best of both worlds – offering a unique value to a significant portion of the market.
Codasip’s proposition means it already has excellent customer traction – it was one of the first companies to commercialize RISC-V IP – but the fact it remains (mostly) a well-kept secret is, from my point of view, a marketing dream come true and a challenge I relish!
May 21, 2021
For about fifty years, IC designers have been relying on different types of semiconductor scaling to achieve gains in performance. Best known is Moore’s Law which predicted that the number of transistors in a given silicon area and clock frequency would double every two years. This was combined with Dennard scaling which predicted that with silicon geometries and supply voltages shrinking, the power density would remain the same from generation to generation, meaning that power would remain proportional to silicon area. Combining these effects, the industry became used to processor performance per watt doubling approximately every 18 months. With successively smaller geometries, designers could use similar processor architectures but rely on more transistors and higher clock frequencies to deliver improved performance.
48 Years of Microprocessor Trend Data. Source K. Rupp.
Since about 2005, we have seen the breakdown of these predictions. Firstly, Dennard scaling ended with leakage current rather than transistor switching being the dominant component of chip power consumption. Increased power consumption means that a chip is at the risk of thermal runaway. This has also led to maximum clock frequencies levelling out over the last decade.
Secondly, the improvements in transistor density have fallen short of Moore’s Law. It has been estimated that by 2019, actual improvements were 15× lower than predicted by Moore in 1975. Additionally, Moore predicted that improvements in transistor density would be accompanied by the same cost. This part of his prediction has been contradicted by the exponential increases in building wafer fabs for newer geometries. It has been estimated that only Intel, Samsung, and TSMC can afford to manufacture in the next generation of process nodes.
With the old certainties of scaling silicon geometries gone forever, the industry is already changing. As shown in the chart above, the number of cores has been increasing and complex SoCs, such as mobile phone processors, will combine application processors, GPUs, DSPs, and microcontrollers in different subsystems.
However, in a post-Dennard, post-Moore world, further processor specialization will be needed to achieve performance improvements. Emerging applications such as artificial intelligence are demanding heavy computational performance that cannot be met by conventional architectures. The good news is that for a fixed task or limited range of tasks, energy scaling works better than for a wide range of tasks. This inevitably leads to creating special purpose, domain-specific accelerators.
This is a great opportunity for the industry.
A domain-specific accelerator (DSA) is a processor or set of processors that are optimized to perform a narrow range of computations. They are tailored to meet the needs of the algorithms required for their domain. For example, for audio processing, a processor might have a set of instructions to optimally implement algorithms for echo-cancelling. In another example, an AI accelerator might have an array of elements including multiply-accumulate functionality in order to efficiently undertake matrix operations.
Accelerators should also match their wordlength to the needs of their domain. The optimal wordlength might not match common ones (like 32-bits or 64-bits) encountered with general-purpose cores. Commonly used formats, such as IEEE 754 which is widely used, may be overkill in a domain-specific accelerator.
Also, accelerators can vary considerably in their specialization. While some domain-specific cores may be similar to or derived from an existing embedded core, others might have limited programmability and seem closer to hardwired logic. More specialized cores will be more efficient in terms of silicon area and power consumption.
With many and varied DSAs, the challenge will be how to define them efficiently and cost-effectively.