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Codasip and Avery Partner to Improve Regression Test Methodology of RISC-V Processors


November 8, 2017

Brno, Czech Republic – November 8th 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced its partnership with Avery Design Systems, the provider of cutting-edge verification intellectual property (VIP) solutions for SoC and IP companies.

Codasip develops licensable RISC-V processors, the Berkelium (Bk) series, via a unique customization tool called Codasip Studio, allowing for fast configuration and optimization of the cores. Studio enables practically an endless number of RISC-V variants, which places extensive demands on verification.

“With the flexibility of Codasip Studio, extensive verification becomes essential, and we are constantly on the lookout for innovative VIP solutions that will make a part of the verification process faster, easier, or more reliable,” says Marcela Zachariášová, the VP of Verification at Codasip. “Avery Design Systems offer some very useful features.”

Specifically, Codasip employs the Avery VIP fault injection feature, which introduces random or precisely-planned faults into the communication lines between the processor and the surrounding components. This allows simulation of unexpected corner cases. Such stress testing is vital to ensure that the processors are robust and reliable even when faults occur.

“We need to ensure that all variants of our RISC-V processors handle error scenarios correctly and can respond to any type of error from the surrounding components without crashing or freezing. Avery’s fault injection helps us analyze such scenarios in our cores,” explains Mrs. Zachariášová.

Codasip itself, and with assistance of industry alliances, has introduced innovations in the field of verification, achieving best-in-class results in verification automation and acceleration. The recent introduction of Avery’s fault injection technology has helped to further improve Codasip’s regression methodology.

“We have partnered with Avery because of unique benefits their fault injection technology brings,” concludes Mrs. Zachariášová.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of an open standard, such as the RISC-V ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About Avery

Founded in 1999, Avery Design Systems, Inc. enables system and SoC design teams to achieve dramatic functional verification productivity improvements through formal analysis applications for RTL and gate-level X verification, and robust verification IPs for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, Unipro, CSI/DSI, Soundwire, and CAN FD standards.

Avery is headquartered in Tewksbury, Massachusetts, and operates an R&D center in Taipei, Taiwan. Avery’s products are directly marketed and distributed in the US, Europe, Japan, Korea, and Taiwan.

For further information about Avery Design Systems, visit www.avery-design.com.

Kava

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Codasip and UltraSoC deliver advanced RISC-V SoC analysis and debug


November 22, 2016

San Jose, CA – Nov 22nd – Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security and debug, announced a broad collaboration to integrate the Codix-Bk series of RISC-V compliant processor cores seamlessly with the UltraSoC environment. As RISC-V based SoCs enter the mainstream, the need for commercial support with production-quality debug, analysis and bring-up tools become critical. This collaboration provides the RISC-V community with capabilities that go beyond those available to proprietary processors and instruction set architectures (ISAs).

While selecting a processor and ISA is one of the first challenges for engineers in architecting a new SoC, the real difficulties come when they try to bring the design to life, to productize and optimize it in the real world. While RISC-V provides an instruction-set architecture for processor IP, it does not in itself solve all the other problems of support, commercialization or development. This partnership focuses on that need. Rather than simply adapt legacy solutions to the RISC-V environment, this collaboration delivers a complete solution that will not only accelerate time-to-market, but extend analysis and improvement capabilities beyond initial deployment.

“Our customers demand more than just traditional processor-based debug in order to meet the needs of the IoT era”, said Karel Masarik, CEO, Codasip, “UltraSoC’s broad range of capabilities combined with our commercially proven processor infrastructure, supported on our RISC-V series of Codix-Bk processors, drastically accelerates SoC deployment. We are excited by what this collaboration enables and the benefits it delivers to the new era of RISC-V based SoC’s”

While RISC-V is establishing itself as the choice for new SoC designs, engineers need proven development infrastructure and commercial support. This collaboration addresees both needs: Codasip provides proven processor IP and infrastructure, while UltraSoC extends this to enable a rich and versatile toolkit for debug, optimization and analytics. This collaboration is an example of how the open-source RISC-V eco-system can innovate quickly to deliver more than is available with legacy proprietary architectures.

“RISC-V is rapidly becoming an exciting ISA choice for new designs, but suffers from the lack of a proven implementation platform”, said Rupert Baines, CEO, UltraSoC, “Combining UltraSoC IP with proven Codix-Bk IP and debug environment results in a powerful SoC debug, analysis and chip-bring up environment that will dramatically accelerate development time while reducing risk for new SoC starts.”

The combined solution is available immediately. Both companies are committed to continually evolve their solutions to conform to the RISC-V foundations specifications (riscv.org).

“RISC-V adoption continues to accelerate with ultimate success requiring the ecosystem evolve beyond initial processor specifications with a focus on the challenges of the SoC creators.”, said Rick O’Connor, Executive Director of the RISC-V Foundation. “We’re excited to see Codasip and UltraSoC working together to make customers RISC-V based designs a reality.”

About Codasip

Codasip delivers leading-edge processor IP technology that provides the advantages of industry standard processor IP with the ability to optimize for your unique application. Codasip’s unique model-based processor IP, and application analysis technology, makes processor customization and optimization available to any design team. As a founding member of the RISC-V foundation (riscv.org) and long term supplier of LLVM and GNU based processor solutions Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe. More information on Codasip’s products and services is available at codasip.com.

About UltraSoC

UltraSoC is an independent provider of SoC infrastructure that enables rapid development of embedded systems based on advanced SoC devices. The company is headquartered in Cambridge, United Kingdom. For more information visit www.ultrasoc.com

About the RISC-V Foundation

RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations under the governance of the RISC-V Foundation. The RISC-V ISA was originally developed in the Computer Science Division of the EECS Department at the University of California, Berkeley.

The RISC-V Foundation, a non-profit corporation controlled by its members, directs the future development and drives the adoption of the RISC-V ISA. Members of the RISC-V Foundation have access to and participate in the development of the RISC-V ISA specifications and related HW / SW ecosystem. riscv.org.

All trademarks are recognized and are the property of their respective companies.

Kava

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