Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Processor design automation to drive innovation and foster differentiation


July 7, 2022

With semiconductor scaling no longer being an option in most situations, optimization means customizing the processor for your specific application. With the right approach and right tools, processor design automation can enable innovation and differentiation. One way of achieving this is to create an application-specific processor by owning the design. To do this efficiently, manual efforts should be reduced to the minimum. Let’s see, in this blog post, how processor design automation can drive innovation and foster differentiation.

RISC-V is bringing design freedom to software and hardware developers

The semiconductor industry is facing scaling limitations (if you haven’t yet, read our white paper on semiconductor scaling) for new applications that require efficient execution of algorithms for data processing. For example, vision, voice and vibration applications. In this context, the only way forward to differentiate is architectural innovation.

The ideal baseline for differentiating is the RISC-V ISA. Free, open, and modular, it allows custom extensions to create a unique processor tailored for specific needs and applications. Most of the time, there is no need to create an entirely new product from scratch. Customizing an existing commercial RISC-V processor is the most efficient way to design a new product with optimal features and PPA.

This approach, which is getting more and more attention, brings new opportunities for software and hardware developers, with complete design freedom. These new opportunities also come with efforts that have not been experienced before. Indeed, any modification to the processor architecture must be reflected in both hardware and software, and be verified. To minimize efforts, make the best use of resources and reduce time to market, processor design automation is key.

Unlocking innovation with processor design automation and Codasip IP and tools

Customization requires the right tools and needs to be considered from the beginning. Codasip RISC-V cores are all designed in CodAL, with customization in mind, so they can be modified seamlessly. Based on C, CodAL is an architecture description language very close to standard programming languages, easy to adopt for processor design automation. This ownership gives you design freedom while keeping control of costs and resources.

Design freedom can start with architecture exploration. Codasip Studio with CodAL generates a Software Development Kit that includes all the tools software programmers will need. Profiling benchmarks, getting performance statistics, making some changes in the design, and seeing the results in just a few minutes: this is all possible with Codasip Studio. But that’s not all.

Codasip Studio workflow
Codasip Studio workflow

Studio and CodAL generate everything needed to be ready for production. Indeed, customization is not just about modifying the RTL. It also includes generating all tools required to design a quality core that can be monetized. Codasip customization solutions take care of this. Customers modify the core as needed in CodAL, the rest is automated.

This unique description language allows the automated generation of the hardware and software tools that are required. With a single, unified toolchain, our customers automatically get the RTL, simulators, testbenches, the verification environment, and a customized compiler that understands their custom hardware and how to take advantage of it. They create a unique product with tools that simplify processor design and verification for all developers.

Processor design automation with Codasip solutions is something we will talk about extensively at DAC 2022 in July, the Design Automation Conference held in San Francisco, California. If you would like to know more about it, visit us at our booth or book a meeting with us.

Visit us at DAC 2022

Lauranne Choquin

Corporate Marketing Manager

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Design for differentiation: architecture licenses in RISC‑V


May 16, 2022

I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp.

In a traditional processor IP model, there is a clear distinction between an off-the-shelf IP license that gives some level of configuration but no customization, and a fairly expensive architecture license enabling a licensee to use the instruction set with their own custom microarchitecture.

With RISC-V, the complication comes from the fact that it is often described as “an open-source architecture”, so people believe that some source code is licensed. But actually that is not the case at all.

Traditional IP and architecture licensing

In a traditional model, things are quite straight forward. A standard license for Arm or MIPS lets the customer use an RTL design but not change it at all (aside from a few configuration options perhaps).

Meanwhile, for customers willing to spend a lot of money, an architecture license gives them the right to modify how a processor executes instructions (the issue width, the cache size, etc.). However, it does not generally give the right to modify the instructions (with some exceptions such as the Cortex-M33 that supports Arm Custom Instructions, allowing the implementation of bespoke data processing operations, or Cadence Tensilica).

RISC-V based IP and architecture licensing

In an open-source model such as RISC-V, things are somewhat different

The RISC-V architecture is usually described as “open-source”, which implies everyone can use it at no cost.

However, a better description of RISC-V is that it is an “open architecture” or “open standard”. In that sense RISC-V is like C, Wi-Fi or LTE with RISC-V International performing the role of (respectively) ANSI, IEEE 802.11 and 3GPP in defining and managing standards that people are free to implement as they choose. But that is a written standard – not an implementation or a microarchitecture.

Just as is the case with those other open standards,  RISC-V licenses can either be open-source or commercial.

You can download open-source designs and have complete freedom to modify them however you wish. Boom, PULP, SweRV and other open-source designs give absolute freedom. But that comes with a cost: they are not supported, the verification is often troublesome, and they may not be of sufficient quality to use in a commercial design. Some companies do use them accepting those compromises; others are understandably wary.

Or you can buy a commercial RISC-V design. There are many companies offering high quality cores delivered as RTL with warranty and full product support. These can be an excellent solution for many customers. Then we are back to something similar to the traditional model: a sort of black box design – although based on an open-standard ISA – in that it cannot be modified or customized to address specific needs. But for many purposes that generic product will be a good fit.

Codasip, as a RISC-V core vendor, does a lot of business on this basis: customers buy a standard RISC-V processor core delivered as RTL and SDK, with high performance, “best-in-class” verification and full support. That is without any architecture license fees, to use it as it is, off the shelf.

ISA customization enables Design for Differentiation

But Codasip offers another option. This is an architecture license – and more – delivered as a source code in the CodAL processor description language.

Many of our customers buy a standard Codasip processor IP product delivered as CodAL source and then use Codasip Studio™  which enables them to modify it freely. We provide the flexibility to modify both the microarchitecture and the ISA, precisely what one needs to Design for Differentiation. Customization at ISA level brings higher performance and optimization. What is more, the power and elegance of the Codasip Studio toolset makes this very easy.

This is different to, for example, an Arm architecture license in three ways:

Freedom

Arm, even with an architecture license, constrains what you are allowed to do. Codasip does not: it is your core and you have control.

Tooling

Arm cores are developed internally, in traditional ways and not designed to be easy to modify. In contrast, all of Codasip’s cores are developed using Studio and are designed expressly to make customization (both ISA and microarchitecture) straightforward and efficient. That includes automatically creating the software toolchain (customized compiler etc) and verification.

Cost

Traditionally the limitation of architecture licenses has been both the cash cost of the license and the engineering resources (cost) required to take advantage of it. Codasip and Studio now make that far easier and hence more affordable with a complete end-to-end architecture customization solution. This dramatically changes the cost equation both of the architecture license fee and the engineering resources required.

RISC-V offers the promise of openness: Codasip and Studio make that promise a reality

Codasip offers the best of both worlds: a portfolio of high-quality standard cores that are a good fit for standard applications, with full verification and support. Or you can upgrade to a cost-effective architecture license, freely customize the core in an easy-to-use environment and have a unique product for your unique needs.

Rupert Baines

Rupert Baines

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Why and How to Customize a Processor


October 1, 2021

Processor customization is one approach to optimizing a processor IP core to handle a specific workload. The idea is to take an existing core that could partially meet your requirements and use it as a starting point for your optimized processor. Now, why and how to customize a processor?

Why you should consider creating a custom core?

Before we start, let’s make sure we are all on the same page. Processor configuration and processor customization are two different things. Configuring a processor means setting the options made available by your IP vendor (cache size, MMU support, etc.). Customizing a processor means adding or changing something that requires more invasive changes such as changing the ISA, writing new instructions. In this blog post we focus on processor customization.

Customizing an existing processor is particularly relevant when you create a product that must be performant, area efficient, and energy efficient at the same time. Whether you are designing a processor for an autonomous vehicle that requires both vector instructions and low-power features, or a processor for computational storage with real-time requirements and power and area constraints, you need an optimized and specialized core.

Processor customization allows you to bring in a single processor IP all the architecture extensions you need, standard or custom, that would have been available in either multiple IPs on the SoC or in one big, energy intensive IP. Optimizing an existing processor for your unique needs has significant advantages:

  • It allows you to save area and optimize power and performance as it targets exactly what you need.
  • It is ready to use. The processor design has already been verified – you only have to verify your custom extensions.
  • You design for differentiation. Owning the changes, you create a unique product.

Now, one may think that this is not so easy. How reliable is the verification of a custom processor? Differentiation is becoming more difficult, time consuming, and sometimes more expensive. The success of processor customization relies on two things:

  • An open-source ISA such as RISC-V.
  • Design and verification automation.

Custom processor, ASIP, Domain-Specific Accelerator, Hardware Accelerator, Application-Specific processor… are all terms related to processor customization.

Customizing a RISC-V processor

Remember: the RISC-V Instruction Set Architecture (ISA) was created with customization in mind. If you want to create a custom processor, starting from an existing RISC-V processor is ideal.

You can add optional standard extensions and non-standard custom extensions on top of the base instruction set to tailor your processor for a given application.

RISC-V Modular Instruction Set. Source: Codasip.

For a robust customization process that ensures quality in the design and confidence in the verification, automation is key.
With Codasip you can license RISC-V processors:

  • In the usual way (RTL, testbench, SDK).
  • In the CodAL source code.

CodAL is used to design Codasip RISC-V processors and generate the SDK and HDK. You can then edit the CodAL source code to create your own custom extensions and modify other architectural features as needed.

Microsemi opted for this approach as they wanted to replace a proprietary embedded core with a RISC-V one. Check this great processor customization use case with Codasip IP and technology!

Processor design automation with Codasip Studio

The legacy approach to adding new instructions to a core is based on manual editing. Adding custom instructions must be reflected in the following areas:

  • Software toolchain.
  • Instruction set simulator.
  • Verification environment.
  • RTL.
Design Automation without Codasip Studio. Source: Codasip.

With the software toolchain, intrinsics can be created so that the new instructions are used by the compiler, but this also means that the application code needs updating. However, modifying the existing ISS and RTL are both potential sources of errors. Lastly, if the verification environment needs changing, this is a further area for problems. Verifying these manual changes is a big challenge and adds risk to the design project.

Some vendors offer partially automated solutions, but by not covering all aspects of processor customization they still leave room for error due to the manual changes.

Design Automation with Codasip Studio. Source: Codasip.

In contrast, with Codasip the changes are only made to the CodAL source code. The LLVM toolchain is automatically generated with support for the new instructions. Similarly, the ISS and RTL are generated to include the custom instructions and can be checked using the updated UVM environment. This approach not only saves time, but is a more robust customization process.

Create an application-specific processor with RISC-V and Codasip

As differentiation is becoming more difficult, time consuming and sometimes more expensive with traditional processor design, customizing a processor so that it will meet your unique requirements is the key. Creating an application-specific processor efficiently, without compromising PPA, requires an open-source architecture and tools to automate the design and verification process. Find out more in our white paper on “Creating Domain-Specific Processors using custom RISC-V ISA instructions”.

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What is the difference between processor configuration and customization?


August 12, 2021

For many years, people have been talking about configuring processor IP cores, but especially with growing interest in the open RISC-V ISA, there is much more talk about customization. So, processor configuration vs. customization: what is the difference?

CPU configuration is like ordering a pizza from the pizzeria

A simple analogy is to think of ordering a pizza. With most pizzerias, you have standard bases and a choice of toppings from a limited list. You can configure the pizza to the sort of taste you would like based on the standard set of options available.

Processor IP vendors have typically offered some standard options to their customers, such as optional caches, tightly coupled memories, and on-chip debug, so that they could combine them and provide the customers with suitable configurations for their needs. While doing so, the core itself remains the same, or has very limited variations. Certainly, the instruction set, register set, and pipeline would remain the same, and only optional blocks such as caches are allowed to vary.

CPU customization is like having a chef making a special pizza for you

Today, many users are demanding greater specialization and variability in their processor cores. This may be to achieve enhanced performance while keeping down silicon area and power consumption. There may be a number of ways in which this can be achieved, for example, by creating custom instructions optimized to the target application, adding extra ports and registers. Such changes fundamentally alter the processor core itself.

Returning to the pizza analogy, customization is like if a private chef has an underlying pizza base recipe but is willing not only to let you provide alternative toppings, but to modify the pizza base, with alternatives to the standard flour, oil, and yeast ingredients used. This is quite a good reason why you would want to customize a processor, isn’t it!

And this is exactly what RISC-V allows you to do. You can customize an existing RISC-V processor to meet your specific requirements by adding optional standard extensions and non-standard custom extensions.

Create a custom core with RISC-V and Codasip

Although some proprietary IP suppliers allow their cores to be extended, the greatest customization opportunity lies with RISC-V. The ISA was conceived from the outset to support custom instructions.Codasip RISC-V processorsCodasip RISC-V Processors were developed using the CodAL architecture description language and are readily customized using Codasip Studio.Codasip StudioFor more information on how custom instructions can be used to create domain-specific processors, download our white paper.

Roddy Urquhart

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What is CodAL?


February 26, 2021

CodAL, standing for Codasip Architectural Language, is central to developing a processor core using Codasip Studio. The language has a C-like syntax and it merges good practices and code constructs from conventional programming languages and hardware description languages. It has been developed from the outset to describe all aspects of a processor including both the instruction set architecture (ISA) and microarchitecture.

Each processor description includes four elements in its description:

  1. Architectural resources, for example, registers and a program counter.
  2. Instruction set, that is, names of instructions, their operands and their binary form (opcodes).
  3. Semantics, or a description of the behaviour of each instruction and exception – how they affect the architectural resources.
  4. Implementation, which includes those resources and behaviour (especially timing) that are not visible in the architectural model but which define a particular micro-architectural implementation. Note that more than one micro-architectural implementation can be in a single CodAL description.

The architectural or instruction accurate (IA) model contains the instruction set, architectural resources, and the semantics. The micro-architectural or cycle accurate (CA) model contains the instruction set, architectural resources and the micro-architectural implementation.

CodAL description. Source Codasip.

CodAL description is object-oriented, meaning that an object can be instantiated into a more complex object, the complex object into an even more complex one, etc. CodAL allows information to be passed through the object hierarchy without having to use complex function calls.

The CodAL element is a common example of an object, and in the following example we show an element describing a multiply-accumulate instruction.

CodAL example. Source Codasip.

The use statement describes the resources that are used by the instruction – a destination register (dst) and two source registers (src1, src2). Next, the assembly statement describes the assembler mnemonic (mac) and its arguments. The binary statement describes the binary representation of the instruction and arguments. Finally, the semantics statement describes the multiply-accumulate operation.

The CodAL description is used by the Codasip Studio toolset to generate an SDK and an HDK. For example, the element description would be used when generating the instruction set simulator (ISS), assembler, disassembler, C/C++ compiler, and debugger for the processor core.

CodAL schema. Source Codasip.

The CA description would take advantage of the instruction set and resources descriptions used for the IA models. In addition, the CA description would specify microarchitectural features such as the pipeline length.

The cycle-accurate parts of the CodAL description would be used for generating the cycle-accurate simulator, RTL, testbench, and UVM environment. In this way CodAL is the single source for all aspects of the processor hardware and software. In contrast, some other processor development tools require two languages to describe the processor core. The methodology also enables powerful verification of generated RTL against a golden reference model in generated UVM environment.

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Customizing an Existing RISC-V Processor


February 11, 2021

Using the open RISC-V ISA is a great starting point for creating a domain-specific processor that combines application-specific capabilities and access to portable software. But how do you create an optimized ISA, profiling software and experimenting with adding/removing instructions, in a smart and easy way? In other words, how do you customize an existing RISC-V processor efficiently?

How to modify the instruction set?

The industry will generally offer you two approaches. Either you do it manually or you automate the process as much as possible.

The manual approach

The old-fashioned way to modify the instruction set would be to:

  1. Modify the instruction set simulator (ISS) to change the ISA.
  2. Update the SDK to reflect the new set of target instructions.

This requires an extensive amount of manual work with associated technical risks. The resulting SDK will almost certainly need to make any custom instructions available as intrinsics or as inline assembler code. The alternative of modifying and verifying the compiler is costly in effort, but the end result is much better for the software developers. Similarly, if a processor is extended, traditionally it would be necessary to modify the microarchitecture by editing the RTL and then verify it against the ISS as the golden reference.

The automated approach

In contrast, describing the ISA in a processor description language like CodAL significantly improves the efficiency of this process using design automation tools. Codasip Studio can automatically generate both the ISS and a new compiler for the modified ISA, making the processor customization process more straightforward. But the CodAL processor description language is not just limited to creating instruction-accurate descriptions – it can also be used to describe microarchitecture (cycle-accurate). The consistency of the two descriptions can be checked within the Studio environment using static analysis.

A far easier approach is to not just to start with the RISC-V ISA, but with a complete RISC-V processor core design described in CodAL.

Automating the customization of a RISC-V CPU with Codasip Studio

Codasip’s RISC-V processors are all designed in Codasip Studio using the CodAL language. The range of cores spans simple 32-bit embedded cores to 64-bit Linux-capable application processors with multi-core capabilities. Thus, you can choose a processor that meets known baseline requirements such as pipeline depth and/or OS support, and then focus on creating custom extensions to improve performance. Starting with an already-proven processor design means that the microarchitecture for any new instructions is incremental, saving time and significantly reducing risk.

Codasip Studio verification flow diagram

Codasip Studio can be used to generate the HDK including the RTL, a testbench, EDA scripts, and a UVM environment. The UVM environment enables the all-important verification of the new processor RTL against its golden ISS reference. The generated UVM environment includes default cover points and assertions for key areas of functionality such as register files, bus protocols, memories, and caches. The third-party RTL simulator can measure the functional and RTL code coverage achieved.

After extending the microarchitecture, Codasip Studio profiler provides coverage analysis tools to assess code coverage of the CodAL, including line, condition, and expression coverage. In order to achieve acceptable code coverage, Codasip Studio provides random assembler generators to exercise the code very thoroughly. In difficult corner cases, it may be necessary to write directed tests.

Diagram that shows the Codasip Studio flow

All-in-all a Codasip RISC-V processor licensed as CodAL source code can be efficiently modified in the Codasip Studio environment and thoroughly verified. This is a cost-effective and super-efficient approach to creating domain-specific processors.

Learn more in our white paper “Creating Domain-Specific Processors with RISC-V custom ISA instructions”.

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How to Choose an Architecture for a Domain-Specific Processor


January 29, 2021

If you are going to create a domain-specific processor, one of the key activities is to choose an instruction set architecture (ISA) that matches your software needs. So where do you start?

Some companies have created their instruction sets from scratch, but if you have such an ISA, a penalty may be the costs of porting software. Today, the RISC-V open ISA can provide you with an excellent starting point and a software ecosystem. Depending on what you need, there are several obvious starting points. In case of a 32-bit processor, if you start with RISC‑V, the base ISA (RV32I) is just 47 instructions. Using this base set is easier than creating proprietary instructions with similar functionality, as well as meaning that software is already available from the RISC-V ecosystem.

Starting point Number of instructions
RV32I 47
RV32IMC 101
RV32GC 164

Many use cases require multiplication suggesting that [M] extensions would be useful, and it is sensible to take advantage of the 16-bit compressed [C] instructions for code density, so it is commonplace to use the RV32IMC set which amount to 101 instructions. Using RISC-V as a starting point will ensure that it is straightforward to use common software such as an RTOS or protocol stack. If you additionally require floating point computation, then the RV32GC (G=IMAFD) instructions may be appropriate, additionally including atomic [A], single-precision floating point [F], and double-precision floating point [D] extensions. Even RV32GC only has 164 instructions.

The RISC-V ISA is designed in a modular way that allows processor designers to add not only any of the standard extensions, but also to create their own custom instructions while keeping full RISC-V-compliance. The standard extensions are a convenient option thanks to being readily available; however, some may substantially increase the instruction set complexity. For example, the complete set of packed SIMD extensions [P] adds 331 additional instructions. In many cases, sufficient gains for a particular application can be made with custom instructions with potentially a lower overhead in silicon area and power.

Having chosen the starting point for your domain-specific processor, it is then necessary to work out what special instructions are needed to meet your computational requirements. This requires a careful analysis of the software that you need to run on your processor core. A profiling tool allows computational hotspots to be identified. Once such hotspots are known, a designer can create custom instructions to address them. Therefore, a designer can iterate by experimenting with adding or deleting instructions, then profiling the software again and assessing whether the changes have achieved their objectives.

However, while this iterative process is logical, how would you actually do it in practice? You might be able to access an open-source instruction set simulator and toolchains such as GNU or LLVM, but modifying these by hand is something for toolchain specialists and is time-consuming.

The alternative is to describe the instruction set using a processor description language. In Codasip Studio, an instruction accurate (IA) model of a processor can be created using the CodAL processor description language. An SDK including compiler, instruction set simulator (ISS), debugger, and profiler can be automatically generated from the IA description.

By describing the ISA at a high level and automatically generating the SDK, it is possible to rapidly iterate experiments in extending the instruction set. In this way, it is possible to choose a well-optimized ISA for a domain-specific processor, sometimes known as an Application Specific Instruction Processor (ASIP). Generating the SDK automatically is not only faster, but less prone to errors than manual changes, meaning that the design process is cheaper and more predictable, avoiding unnecessary risk and roadmap disruptions.

Roddy Urquhart

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More than Moore with Domain-Specific Processors


May 6, 2020

Last month was the 55th anniversary of Gordon Moore’s famous paper Cramming more components onto integrated circuits. He took a long-term view of the trends in integrated circuits being implemented using successively smaller feature sizes in silicon. Since that paper, integrated circuit developers have been relying on three of his predictions:

  1. The number of transistors per chip increasing exponentially over time.
  2. The clock speed increasing exponentially.
  3. The cost per transistor decreasing exponentially.

These predictions have largely held true for almost half a century, enabling successive generations of processors to achieve higher computational performance through greater processor complexity and higher clock speeds. These improvements were mainly delivered through general-purpose processors implemented in new technology nodes.

From about 2005, the improvements in clock frequency began to level off, leading to a levelling-off of single thread performance. Since then, using multiple cores on a single die has become commonplace, but again these cores were mainly general-purpose ones, whether application processors or MCUs.

If you are designing a chip with some performance challenges, do you simply follow Moore’s law and move into a smaller silicon geometry and use general-purpose processor cores? That could be a costly approach since mask-making costs are higher in small geometries. Also, you may not achieve your performance in the most efficient way.

Many embedded applications involve cryptography, DSP, encoding/decoding or machine learning. Each of these operations typically run inefficiently on a general-purpose core. For example, Galois fields are commonly used in cryptography, but multiplication operations take many clock cycles.

So, what can be done to deal with computational bottlenecks? In extreme cases, like dealing with real time video data, it may make sense to create dedicated computational units to handle a narrow range of computationally intensive operations. However, this may not be the best trade-off.

It will often be desirable to run both computationally intensive operations and other embedded functions on the same processor core.  Ideally, the most silicon-efficient processor implementation will be one that is tuned for your particular application.

This can be achieved by creating a processor core that has custom instructions targeted to address the bottlenecks. Adding custom instructions does not have to be expensive in silicon resources. For example, Microsemi created custom DSP instructions for their RISC-V-based audio processor products: Their custom Bk RISC-V processor delivered 4.24× the performance of the original RV32IMC core but required only a 48% increase in silicon area. Furthermore, the code size shrunk to 43% of the original size1.

So how can you efficiently implement custom instructions? And equally importantly, how do you verify that they are implemented correctly? We will be visiting these topics on future posts.

1 Dan Ganousis & Vijay Subramaniam, Implementing RISC-V for IoT Applications, Design Automation Conference 2017

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Codasip Releases Studio 8, a Breakthrough in RISC-V Automation, and the Bk7 RISC-V Processor Core for Real-Time Computing Applications


December 6, 2018

Munich, Germany – December 6th, 2018 – CodasipGmbH, the leading supplier of RISC-V® embedded processor IP, announced today the latest version of Studio, a suite of tools optimized for the development and verification of RISC-V processors, and the Bk7 processor, the first Codasip RISC-V core optimized for Linux and real-time performance.

“As the RISC-V ISA specification evolves and adds an ever-increasing number of optional architecture extensions, a processor design methodology that allows for both rapid architectural exploration and simplified creation of easily implementable RTL becomes essential,” stated Chris Jones, Vice President of Marketing at Codasip. “What is needed is a high-level processor description language optimized for RISC-V, so Codasip has delivered Studio 8, a comprehensive tools suite for RISC-V processor development.”

With Studio, designers write a high-level description of a processor in CodAL, an architecture description language, and then automatically synthesize the design’s RTL, test bench, virtual platform models, and processor SDK (C/C++ compiler, debugger, profiler, etc.). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.

Codasip employs this silicon-proven methodology to create and deliver a broad portfolio of licensable RISC-V processor IP.  Through these product developments, Studio has evolved to make it more suitable for implementing and extending the instruction set of RISC-V cores. The 8th generation of Codasip Studio, just announced, adds significant new functionality and features, making it the most advanced and effective technology on the market for tailoring RISC-V processors to meet chip designers’ application-specific needs. Specifically, Studio 8 includes:

  • Support for LLVM debugger (LLDB) and OpenOCD,
  • LLVM 7.0,
  • Studio/CodeSpace IDEs based on Eclipse Oxygen along with more interactive consoles,
  • improved test suites and verification to better support user-defined RISC-V extensions.

Further, Codasip architects employed Studio to develop the Bk7 processor, the latest RISC-V micro-architecture in the Codasip portfolio.

A 64-bit machine featuring a balanced 7-stage pipeline with branch prediction, optional full MMU with virtual addressing support for operating systems such as Linux, and support for the popular RISC-V standard extensions as well as industry-standard external interfaces, the Bk7 is Codasip’s highest-performance processor to date and is ideal for system-on-chip designers who need the right balance of power and performance.  Also, the Bk7 is fully customizable so architects can easily add additional instructions, registers or interfaces. And as with each member of the Codasip Bk processor family, the Bk7 comes with the following deliverables:

  • Readable Verilog or VHDL RTL along with test benches and synthesis scripts,
  • SDK consisting of LLVM-based compiler, advanced profiling and debugging tools,
  • both cycle-accurate and fast instruction-accurate simulation tools.

Studio 8 and the Bk7 processor are generally available in the first quarter of 2019, with early access to selected customers immediately.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 with research and development located in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. Codasip is currently venture-backed by Credo Ventures, Ventech Capital, Shenzhen Capital, Paua Ventures, and Western Digital.

For more information about Codasip’s products and services, visit codasip.com.

About RISC-V

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open-standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

For more information about RISC-V, visit www.riscv.org.[/cs_text][/cs_column][/cs_row][/cs_section][/cs_content]

Kava

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