by Tora Fridholm
This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the same weather but Munich was up for the challenge and served us a sunny, hot week, only interrupted by a thunderstorm that shook up some conference attendees (including me!) on the Wednesday afternoon. However, thunderbolts and lightning were also present in a less literal form as massive applause following the many talks, and an abundance of photos and selfies taken in the expo hall and at the social events.
AI, AI, AI…
Of course, AI is a hot topic and was mentioned probably in most of the presentations. I very much appreciated the keynote by Edward Wilford, analyst at Omdia. Edward talked about ”The intelligent wave: How a growth in advanced and accelerated compute will drive adoption of RISC-V.” I really enjoyed hearing his angle on generative AI not being a solution. Whereas embedded AI, on the edge, is where it’s getting interesting. Edward described embedded AI as AI you have control over, and encouraged the community to sell AI for what it can do: it’s a feature, not a product.
This ties in well with the demo at the Codasip booth of AI inference for anomaly detection on an embedded RISC-V core. We actually did the same demo at DAC in San Francisco and you can watch a video of this Codasip L110 demo here.
Pioneering next-generation automotive
The topic of AI-driven anomaly detection brings me to another highlight of RISC-V Summit Europe this year: the Wednesday morning keynote by Thomas Böhm, Senior Vice President & General Manager Microcontroller Automotive at Infineon Technologies. Thomas said AI will drive automotive feature disruption in the next decade. He also pointed out there is still much innovation to be done in the automotive industry for example related to safety and security features. This innovation will come from technologies such as accelerators enabled by RISC-V.
The strong trend of RISC-V driving innovation in automotive was also highlighted in talks by Bosch and Quintaris. It’s clear, RISC-V is here to stay in automotive and this trend is only getting started.
Several projects are working on increasing alignment and securing long-term support for RISC-V.
All the CHERI you can eat
At Codasip, we have invested in creating the first commercial implementation of the memory safety technology CHERI so obviously we see the great potential in this innovation from the University of Cambridge. At the Summit, CHERI was a hotter topic than ever and included in presentations and posters from lowRISC, the University of Cambridge, Minerva, and the University of Minho. Also SiFive’s Krste Asanovic talked about CHERI bringing capabilities to RISC-V in his State of the Union address.
Our Chief Architect Tariq Kurd had a presentation on standardizing CHERI for RISC-V. However, he hijacked his own presentation to go off script on a CHERI FAQ based on all the discussions he had during the conference. With a major delegation from the University of Cambridge present, Tariq was spot on in his opening statement: It’s safe to say any questions you have about CHERI can be answered by someone who is currently in this room.
And that is also a very nice way to wrap up this brief summary. With such a major gathering of RISC-V enthusiasts at the same event, you had ample opportunity to get questions answered, but the inspiring conversations also generated new ones. These fresh inquiries will surely spark ideas for presentations at the next event. All of us here at Codasip are looking forward to it!
