Codasip Studio 9.2.0: what’s new?
September 5, 2022
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September 5, 2022
Codasip Studio in its 9.2.0 release is now available. This new version of our unique processor design automation toolset comes with a series of new features that both expand and optimize its applications.
The new features supported in Codasip Studio 9.2.0 include:
Let’s have a look at the macro processor, uRISC-V 2.0, and arrays in CodAL features.
Codasip Studio 9.2.0 includes a macro processor, that is, a powerful text processor that simplifies the writing of CodAL models by using a set of constructs for generating the code. Compared to a C/C++ preprocessor, it supports major features such as callable macros with arguments, loops, and complex expressions, among others.
The macro processor simplifies the work of developers as it avoids repeating efforts and calling functions that could create unnecessary overheads. The following example shows a possible usage of the macro processor.
Note that the macro processor can also be used with other languages and tools.
Codasip Studio 9.2.0 supports arrays of registers and register files for multi-threaded cores. These arrays hold the information on a per thread basis. The size of the arrays matches the number of threads and each thread only includes its respective index in the array that is available for use.
Note that arrays of signals are also supported in Codasip Studio 9.2.0, however they always have the same size and multi-dimensional arrays are not supported. Array-to-array assignment is supported as long as the data type matches one-to-one, even if the resource type is different. For example, assigning an array of registers to an array of signals of the same data type is supported.
Arrays can be dynamically indexed. In the case of loops, semantics are extended so they can be used with arrays.
The following example shows the array syntax for architectural resources.
register bit r_foo ;
register_file bit rf_foo [FOO_SIZE];
register bit s_foo [ONE + TWO];
Codasip Studio 9.0 first supported the uRISC-V processor for 5-stage pipeline applications. uRISC-V is a tutorial that allows users to inspect and learn on a real RISC-V implementation. In Codasip Studio 9.2.0, this tutorial becomes uRISC-V 2.0 is now available also for 3-stage pipeline applications.
This feature extends the possibilities both for educational purposes or for familiarization with the RISC-V architecture in Studio. It includes experimenting with modifying the processor, adding custom instruction extensions, and optimizing performance in a model that has been designed with the same methodology as the Codasip RISC-V commercial cores.
The implementation is a simple 32-bit or 64-bit 3-stage pipeline processor that supports the RISC-V I (Base Integer), M (Standard Extension for Integer Multiplication and Division), Zicsr (Control and Status Register instructions) and Zifencei (fence instructions) extensions as well as the RISC-V standard based On-Chip Debugger.