Customization? Yes! After tape-out? Yes!
Another RISC-V Summit is behind us. It was a very well-attended event with many exciting talks and companies highlighting their products at the exhibition. One of the main themes was, once again, customization. Many people and companies, including Meta in their keynote, insisted on the importance of customization and how this key aspect of the […]
Configurable LLDB for (not only) embedded RISC-V processors
At some point, software developers or processor developers need to check and debug their code. They can do this at different levels, for example looking at waves or parsing printouts, but the preference is to check code in an interactive session. The debugger facilitates the interactive session by accepting developers’ commands, executing them, and showing […]
Re-targetable LLVM C/C++ compiler for RISC-V
RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions are many: better performance, smaller […]
Codasip Studio 9.2.0: what’s new?
Codasip Studio in its 9.2.0 release is now available. This new version of our unique processor design automation toolset comes with a series of new features that both expand and optimize its applications. The new features supported in Codasip Studio 9.2.0 include: Macro Processor. Arrays in CodAL. uRISC-V 2.0. Pipeline definition in modules. Simulator Save state and […]