DAC 2022 – Is it too risky not to adopt RISC-V?
I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve been going to DAC since 1995. Many people, including me, arrived to the San Francisco with a bit of trepidation. After all, 58th DAC had low attendance and it was […]
Embedded World 2022 – the RISC-V genie is out of the bottle
The last Embedded World was back in February of 2020, but the event was hit hard by Covid-19 with many exhibitors and visitors deciding to pull out last minute. No-one knew then that it would take almost two and half years before the embedded industry would regroup again in Nuremberg. Even now, in June 2022, […]
A European Opportunity for Codasip
Why did I join Codasip a couple of days ago as VP of Sales for EMEA? We could sit down here and discuss for a few hours, but perhaps I should keep it short for now. Number 1: The RISC-V revolution is happening and Codasip is one of the leaders in the industry. Number 2: […]
Three Reasons why Codasip Women Engineers are Awe-inspiring
With International Women’s Day behind us and International Women in Engineering Day on June 23rd, we wanted to put great women in engineering on the spotlight. But no Ada Lovelace or Hedy Lamarr in this article. Computer science is constantly evolving, becoming increasingly important in our world, and there are so many reasons for women […]
RISC-V Summit 2021 highlights
Semiconductor scaling is failing to meet designers’ needs, customers want more heterogeneous compute” and “domain specific acceleration”
It’s time to join Codasip and the RISC-V revolution
Customization arises from optimizing a processor IP core to handle a certain workload. In some case it makes sense to design a dedicated core from scratch, but in many cases an existing core may partially meet your requirements and can be a good starting point for your optimized core.