Rambus Selects Codasip Studio for SDK Development of RISC-V Processor
Codasip Studio Enables Fully Automated Development of the Processor Software Design Kit While Saving Significant Time and Resources Brno, Czech Republic – November 14th 2017 – Codasip, Ltd., the leader in RISC-V embedded processor IP cores, today announced that Rambus selected Codasip Studio for developing its next-generation RISC-V security products. Codasip Studio provides fully automated generation […]
Codasip and Avery Partner to Improve Regression Test Methodology of RISC-V Processors
Brno, Czech Republic – November 8th 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced its partnership with Avery Design Systems, the provider of cutting-edge verification intellectual property (VIP) solutions for SoC and IP companies. Codasip develops licensable RISC-V processors, the Berkelium (Bk) series, via a unique customization tool called Codasip Studio, allowing for fast configuration and optimization […]
Codasip Announces Latest RISC-V Processor
The Newest Codasip RISC-V Processor is Ideal for IoT Designs Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) […]
A Tale of Two Approaches to High-Performance IoT
EXTENSIBLE PROCESSORS VS ACCELERATORS – AND HOW RISC-V CHANGES THE DYNAMIC If you were to ask any good designer today what is the best architecture for an SoC that needs to manage complex DSP or high bandwidth traffic demands – you will almost always find the recommendation of using one or more off-the-shelf processors, complimented […]
Codasip and UltraSoC collaborate on RISC-V trace support
UltraSoC today announced its work on adding trace functionality to the RISC-V specification, and Codasip along with 4 other IP vendors have pledged support. Read more in the announcement at http://www.ultrasoc.com/ultrasoc-announces-industrys-first-processor-trace-support-risc-v/
Codasip and TVS Deliver Advanced RISC-V Verification Solutions
Brno, Czech Republic – March 10th 2017 – Codasip, a leading RISC-V processor IP provider, and T&VS (Test and Verification Solutions), a leading verification services provider for semiconductor IP, hardware and software, today announced a broad collaboration to accelerate the verification of products based on the Codix-Bk series of RISC-V compliant processor cores. The partnership […]
BaySand, Codasip, Codeplay and UltraSoC accelerate IoT development with “silicon-to-intelligence” RISC-V platform
MOUNTAIN VIEW, CA, 29th November 2016 BaySand, Codasip, Codeplay and UltraSoC today announced an integrated IoT development platform based on the RISC-V open processor instruction set architecture (ISA). The platform offers an open-standards-based solution that allows designers of systems-on-a-chip (SoCs) for IoT applications to get from concept to silicon with a high level of software […]
Codasip and UltraSoC deliver advanced RISC-V SoC analysis and debug
San Jose, CA – Nov 22nd – Codasip, the leading RISC-V processor IP provider, and UltraSoC, the leading provider of semiconductor IP for on-chip analytics, performance optimization and hardware-based security and debug, announced a broad collaboration to integrate the Codix-Bk series of RISC-V compliant processor cores seamlessly with the UltraSoC environment. As RISC-V based SoCs […]
Codasip and BaySand Partnership Makes RISC-V-Based ASICs an Ideal Choice for IoT Designs
San Jose, CA – Nov 9th 2016 – Codasip, a leading-edge processor IP provider, and BaySand, the leader in application configurable ASICs, announced that they are collaborating to make the Codix-Bk series of RISC-V compliant processor cores available on BaySand’s new UltraShuttle service in 65nm and 40nm. RISC-V is becoming a pivotal processor standard for […]