Meet us at the RISC-V in Space workshop on 14 December, 2022, at the Erasmus Auditorium at European Space Research and Technology Centre (ESTEC) in Noordwijk, Netherlands.
Our talk
Mike Eftimakis, our VP of Strategy and Ecosystem, is doing a presentation jointly with Menta on RISC-V processor customization.
When: Wednesday 14th December, 2022
Where: Erasmus Auditorium at ESTEC – ESA, Noordwijk, Netherlands
Presentation: RISC-V processor customization in the field
Country Manager, Japan Takaaki Akashi will be presenting a series of talks at the event.
Make your own RISC-V story – Design for differentiation. Nov 17th – 15:20-15:50 Pacifico Yokohama, North 3F, G313
It’s not open source! The true value of open standard instruction set (ISA) RISC-V. Nov 18th – 11:15-11:45 Pacifico Yokohama Exhibition Hall-C Center-stage A
Meet the team
Come and visit us to learn more about RISC-V with a twist! Akashi-san, Ito-san, and Brett Cline will be there.
We are a platinum sponsor of the RISC-V Summit 2022 taking place in San Jose, California, US, on 13-14 December, 2022.
Stop by our booth to see demos of our latest technology and meet the team.
Codasip talks
Ron Black, CEO
RISC-V Spotlight
Avoiding Murphy’s Law and Satan’s Law without selling your soul
Tuesday, December 13, 10:35am – 10:45am
No one knows Murphy’s Law of “anything that can go wrong will go wrong” better than automotive OEMs who always must assume this to be true and create systems with safety in mind for any and all risks of system failure. But with connected cars, there is a new law to consider: Satan’s Law. As an automotive manufacturer, you must now also assume all people are bad and want to hack your system. Much is to gain by adopting an integrated approach that can provide a complimentary safety and security solution that is scalable in either direction while balancing PPA.
Paul Elliott, Safety and Security Architect
Demo
RISC-V dual lock-step implementation for safety and security applications
Tuesday, December 13, 3:30pm – 3:40pm
In this session, we demonstrate how a secure dual-core lockstep processor can be used to detect and trap faults injected at the hardware level, no matter if that fault was caused by a system malfunction or a deliberate attack. To enable fault testing the design is annotated with smart fault injectors, a functionality that Codasip intends to provide to automate and aid the design of resilient compute systems. The smart fault injectors can be adapted to different fault models addressing the automotive functional safety ISO 26262:2018 as well as the automotive cybersecurity standard ISO/SAE 21434:2021. A proven method in other architectures, dual lockstep enables fault detection no matter what caused the fault.
Keith Graham, VP University Program and Customer Experience
Stefan Wallentowitz, Munich University of Applied Sciences Sarah Harris, University of Nevada in Las Vegas Michael Engel, University of Bamberg
Panel
RISC-V in education and training: Successes and gaps
Wednesday, December 14, 4:25pm – 5:10pm
RISC-V has a strong academic background and was early adopted by many universities, and a industrial training partners are part of the RISC-V academia and training ecosystem. While the availability of hardware has been an issue for a couple of years, options slowly become available. This panel of distinguished members of the RISC-V education community is organized by the Special Interest Group on Academia and Training and we will briefly give an overview of the state of the ecosystem. The introduction is followed by a discussion of the available materials, tools and frameworks, along with an open discussion around gaps and challenges around education and industrial training.
