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RISC-V In Space


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14/12/2022

Meet us at the RISC-V in Space workshop on 14 December, 2022, at the Erasmus Auditorium at European Space Research and Technology Centre (ESTEC) in Noordwijk, Netherlands.

Our talk

Mike Eftimakis, our VP of Strategy and Ecosystem, is doing a presentation jointly with Menta on RISC-V processor customization.

When: Wednesday 14th December, 2022

Where: Erasmus Auditorium at ESTEC – ESA, Noordwijk, Netherlands

Presentation: RISC-V processor customization in the field

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Osmosis formal verification conference


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08/12/2022

Meet us in Munich, Germany at the Siemens formal verification conference.

Our talks

Philippe Luc, our Director of Verification, will give a presentation on How formal lights up your RISC-V verification avenue.

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06/12/2022 to 07/12/2022

Meet Codasip at DVCon Europe in Munich!

Our talks

Philippe Luc, our Director of Verification, is doing a presentation jointly with Siemens on RISC-V verification.

When: Wednesday 7th December, 2022

Time: 15:45 – 16:15, local time

Where: Forum 5

Presentation: 75659 – How the Right Mindset Increases Quality in RISC-V Verification

Just after his talk, Philippe Luc will also be on a panel to discuss ‘Are processor/SoC discontinuities turning verification on its head?‘.

When: Wednesday 7th December, 2022

Time: 16:45, local time

Where: Ballsaal Room

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IP SoC Conference 22


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30/11/2022 to 01/12/2022

Meet Codasip at the IP SoC Days in Grenoble, France!

We are a bronze sponsor of the event, stop by our stand and speak with our team.

Our talks

Mike Eftimakis, our VP Strategy and Ecosystem will give a keynote on November 30th.

Meet the team

Both Mike and Emmanuel Till-Vattier, our VP Sales EMEA, will be at the conference. Don’t miss a chance to talk to them.

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21/11/2022 to 22/11/2022

Meet Codasip at Cadence Live in Munich in November!

Our talks

Premysl Vaclavik our Senior Director of Open IP, will give a talk on using physical synthesis and physical tools in RISC-V IP development flow.

His talk is on November 22nd, 2022, 14:30-15:00 local time.

Meet the team

Emmanuel Till-Vattier, our VP Sales EMEA will also be at the conference. Don’t miss a chance to speak with him and Premysl!

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RISC-V Days Tokyo


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16/11/2022 to 18/11/2022

Meet Codasip at the RISC-V Days in Tokyo in November!

Visit the team at our Codasip stand.

ブースC-B15 に@Codasip出展しております RISC-V にご興味をお持ちの方、是非お立ち寄り下さい

Our talks

Country Manager, Japan Takaaki Akashi will be presenting a series of talks at the event.

Make your own RISC-V story – Design for differentiation.
Nov 17th – 15:20-15:50
Pacifico Yokohama, North 3F, G313

It’s not open source! The true value of open standard instruction set (ISA) RISC-V.
Nov 18th – 11:15-11:45
Pacifico Yokohama Exhibition Hall-C Center-stage A

Meet the team

Come and visit us to learn more about RISC-V with a twist! Akashi-san, Ito-san, and Brett Cline will be there.

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26/12/2022 to 27/12/2022

Codasip诚邀您光临中国集成电路设计2022年会暨厦门集成电路产业创新发展高峰论坛(ICCAD 2022)

时间:2022年12月26-27日
地点: 厦门国际会展中心
展位:C2馆362号展位

Codasip ICCAD IP & IC 设计服务专题论坛演讲半导体定律逐渐失效,SoC的未来将如何?

时间:2022年12月27日 15:50 – 16:10
地点: 厦门国际会展中心 304 会议室

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RISC-V Summit 2022


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See you in San Jose13/12/2022 to 14/12/2022

We are a platinum sponsor of the RISC-V Summit 2022 taking place in San Jose, California, US, on 13-14 December, 2022.

Stop by our booth to see demos of our latest technology and meet the team.

Codasip talks

Ron Black, CEO

RISC-V Spotlight

Avoiding Murphy’s Law and Satan’s Law without selling your soul

Tuesday, December 13, 10:35am – 10:45am

No one knows Murphy’s Law of “anything that can go wrong will go wrong” better than automotive OEMs who always must assume this to be true and create systems with safety in mind for any and all risks of system failure. But with connected cars, there is a new law to consider: Satan’s Law. As an automotive manufacturer, you must now also assume all people are bad and want to hack your system. Much is to gain by adopting an integrated approach that can provide a complimentary safety and security solution that is scalable in either direction while balancing PPA.


Paul Elliott, Safety and Security Architect

Demo

RISC-V dual lock-step implementation for safety and security applications

Tuesday, December 13, 3:30pm – 3:40pm

In this session, we demonstrate how a secure dual-core lockstep processor can be used to detect and trap faults injected at the hardware level, no matter if that fault was caused by a system malfunction or a deliberate attack. To enable fault testing the design is annotated with smart fault injectors, a functionality that Codasip intends to provide to automate and aid the design of resilient compute systems. The smart fault injectors can be adapted to different fault models addressing the automotive functional safety ISO 26262:2018 as well as the automotive cybersecurity standard ISO/SAE 21434:2021. A proven method in other architectures, dual lockstep enables fault detection no matter what caused the fault.


Keith Graham, VP University Program and Customer Experience

Stefan Wallentowitz, Munich University of Applied Sciences
Sarah Harris, University of Nevada in Las Vegas
Michael Engel, University of Bamberg

Panel

RISC-V in education and training: Successes and gaps

Wednesday, December 14, 4:25pm – 5:10pm

RISC-V has a strong academic background and was early adopted by many universities, and a industrial training partners are part of the RISC-V academia and training ecosystem. While the availability of hardware has been an issue for a couple of years, options slowly become available. This panel of distinguished members of the RISC-V education community is organized by the Special Interest Group on Academia and Training and we will briefly give an overview of the state of the ecosystem. The introduction is followed by a discussion of the available materials, tools and frameworks, along with an open discussion around gaps and challenges around education and industrial training.

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