How to exhaustively verify that your custom instructions aren’t secretly breaking your RISC-V design
The last thing you want to do when adding custom instructions to your RISC-V design is to unintentionally insert some deep corner case bug – the kind of bug that’s discovered by your customers a month after the end-product has shipped.
Simulation-based verification approaches find many common errors; but to be really sure that there are no hidden side-effects or “specification bugs”, an exhaustive, formal-based verification flow is also needed.
In this presentation we will guide you through the simple design and verification steps you can take to combine simulation and formal approaches; with a particular emphasis on leveraging automated, formal-based sequential equivalence checking (SLEC). These methodologies will be illustrated with real-world case studies.
This is a joint webinar with Siemens EDA.
What you will learn:
- RISC-V customization principles
- An efficient design automation and customization flow for RISC-V processors
- Processor design in a high-level description language
- Going from high-level description language to RTL generation
- A light-weight formal verification flow targeted towards customization
Who should attend:
- Design engineers
- Design verification engineers
- Formal verification engineers
- Verification managers
- RISC-V enthusiasts
Which products are covered:
- Codasip Studio design automation toolset
- Codasip CodAL processor description language
- Codasip L31 RISC-V embedded processor
- Siemens Questa OneSpin Processor Verification App
- Sven Beyer, Program Manager, Processor Verification, Siemens EDA
- Laurent Arditi, Formal Verification Lead, Codasip
- Zdenek Prikryl, CTO, Codasip