RISC-V Summit US 2023

This November, the global RISC-V community including our Codasip team of RISC-V experts will meet in Santa Clara, California to share technology breakthroughs, industry milestones, and case studies. Will you be there? Let’s meet!

Codasip diamond sponsor of RISC-V summit 2023 in Santa Clara USA

We transform how the world designs processor through a unique custom compute approach. With the combination of customizable secure RISC-V IP and Codasip Studio, our EDA toolset, you can create the perfect product tailored to your needs.

Let’s talk safe and secure customizable IP

Throughout this US RISC-V summit we will present and take the time to discuss with you our Custom Compute approach to offer you safe and secure customizable IP that will meet your specific needs.

Technical talks

IMU sensor ML action detection optimization with custom instructions on embedded RISC-V cores

By Peter Robertson 

Tuesday November 7 – 11:30 PST

Join this talk that will highlight how a small RISC-V based processor with the addition of custom instructions, in conjunction with an IMU sensor providing input data for the model, can be practically used as an AI inference platform for activity detection in a real-life use case. By the end of the session, you will understand how this can be efficiently achieved and made possible using processor design automation.

Code Size Reduction Deep Dive: Zc Extensions and Dictionary Compression Custom Instruction

By Tariq Kurd

Wednesday November 8 – 11:30 PST

Code size is a critical metric in embedded CPU systems because of its direct impact on silicon area. In this presentation, we will examine the code-size reductions that are possible using the Zc extensions proposed by the RISC-V Code Size Reduction Task Group. These improvements can make RISC-V competitive with legacy CPU architectures. We will demonstrate how Zc saves about 12.5% on average across the benchmark suite, plus further savings thanks to the addition of a custom instruction.

Technical poster

CHERI-RISC-V from academia to industry: Memory safety without rewriting your C/C++ software

By Carl Shaw (in collaboration with Cambridge University)

Posters will be in the exhibition hall of the US RISC-V Summit. Come and talk to Carl to understand how easy it is to port code to use CHERI protections given current toolchain support for CHERI-RISC-V. He will tell you about how CHERI integrates and can co-exist with other RISC-V extensions, along with the current challenges. And why not ask Carl about how standardization and industry adoption of CHERI can bring significant benefits to safety and security?

Demos at the theatre

After his talk, Peter will also do a demo in the theatre of the conference on optimizing ML for IMU sensor action section.

On his side, Zdenek Prikryl will do a demo on RISC-V as an enabler of heterogeneous compute.

We are also working on demos for you at our booth. Stay tuned.


Innovation secure: a paradigm shift in the processor industry

By Ron Black, CEO

Comprehensive memory protection is a concern for all processor and SoC designers, device manufacturers, OEMs, and end users. How can we, today, revisit fundamental design choices in hardware and software to improve system security?

You know what you need. We will help you get there.

Think about it, and talk to us.

Book a meeting with us at RISC-V Summit 2023

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