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RISC-V architecture

What is the RISC-V architecture?

The RISC-V instruction set architecture (ISA) is an open standard which is owned and maintained by RISC-V International.

The ISA is based on reduced instruction set computer (RISC) principles and provides definitions for 32- and 64-bit word lengths. Unlike most other RISC ISAs, RISC-V is modular allowing for a base integer instruction set, standard extensions and custom extensions.


How is the RISC-V architecture developed and maintained?

The RISC-V architecture is developed and maintained by RISC-V International, which is a non-profit organization that oversees the development, promotion, and support of the RISC-V ISA.

More than 3,000 RISC-V members across 70 countries, including Codasip, contribute and collaborate to define RISC-V open specifications. The development and maintenance of the RISC-V architecture is done through different activities and at different levels. For example:

  1. Technical committee: A technical committee composed of experts from member organizations is responsible for overseeing the evolution and development of the RISC-V ISA. It manages proposals, reviews, changes and additions to the ISA specification.
  2. Working groups: These groups focus on specific areas of the architecture and collaborate on topics such as vector extensions, security extensions, debug support, and other aspects. Codasip has several members in these groups: Paul Elliott, Safety and Security Architect, is chair of the Security Model group. Our safety and security team is also actively involved in the CHERI SIG and Functional Safety SIG groups.
  3. Ecosystem collaboration: Companies, organizations, and individuals in the RISC-V ecosystem can contribute to the development of software tools, compilers, operating systems, development boards, and other components that support the RISC-V architecture.

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