Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

处理器定制

[cs_content][cs_element_section _id=”1″ ][cs_element_layout_grid _id=”2″ ][cs_element_layout_cell _id=”3″ ][cs_element_text _id=”4″ ][cs_content_seo]Processor Customization
Jump-start with an existing design\n\n[/cs_content_seo][cs_element_text _id=”5″ ][cs_content_seo]Customizing an existing design is the most convenient way to your custom processor core, tailored for the intended domain. Our smart technology with highly automated workflow guarantees fast results with minimal manual effort.\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”6″ ][cs_element_layout_grid _id=”7″ ][cs_element_layout_cell _id=”8″ ][cs_element_button _id=”9″ ][cs_content_seo]The architecture: RISC-V\n\n[/cs_content_seo][cs_element_button _id=”10″ ][cs_content_seo]The tool: Codasip Studio\n\n[/cs_content_seo][cs_element_button _id=”11″ ][cs_content_seo]Customer use case\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”12″ ][cs_element_text _id=”13″ ][cs_content_seo]If you need to optimize a processor IP core to handle a certain workload, you need to customize. In some case it makes sense to design a dedicated core from scratch, but in many cases an existing core may partially meet your requirements and can be a good starting point for your optimized core.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”14″ ][cs_element_headline _id=”15″ ][cs_content_seo]Why Customize?\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”16″ ][cs_element_layout_grid _id=”17″ ][cs_element_layout_cell _id=”18″ ][cs_element_text _id=”19″ ][cs_content_seo]RISC-V is an open ISA (Instruction Set Architecture) that has been created with customization in mind, and is therefore ideal for the job.
The RISC-V instruction set has three classes of instruction: There is a base instruction set for a given wordlength (32-, 64- or 128-bit), different groups of optional standard extensions and non-standard custom extensions.
There is a large part of the opcode space which is available for custom extensions. A processor architect can use such extensions to deliver extra processing performance to address a given computational workload.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”20″ ][cs_element_text _id=”21″ ][cs_content_seo]How to Customize
Using the Power of RISC-V\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”22″ ][cs_element_image _id=”23″ ][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”24″ ][cs_element_layout_grid _id=”25″ ][cs_element_layout_cell _id=”26″ ][cs_element_headline _id=”27″ ][cs_content_seo]Codasip StudioTool for the job\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”28″ ][cs_element_text _id=”29″ ][cs_content_seo]Codasip Studio is a market-unique suite of tools for automating the design of programmable cores using the CodAL architecture description language. The technology is particularly synergistic with the RISC-V ISA (although it can be applied to cores based on any other ISA too). It provides two approaches to implementing the custom instructions in hardware:

Implementing the logic in the processor pipeline,
Connecting a co-processor with a generated interface.

Some processor IP vendors, too, offer tools and extensible cores which allow a limited amount of customization. However, Codasip Studio offers far more freedom, both in terms of ISA and microarchitecture.\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”30″ ][cs_element_layout_cell _id=”31″ ][cs_element_headline _id=”32″ ][cs_content_seo]How others do it\n\n[/cs_content_seo][cs_element_text _id=”33″ ][cs_content_seo]When it comes to RISC-V customization, most tools on the market rely on manually edited or additionally provided code to the original RTL and tools. This approach is risky, lengthy, unsuitable for flexible changes, and potentially unable to take full advantage of any added custom instructions.\n\n[/cs_content_seo][cs_element_image _id=”34″ ][/cs_element_layout_cell][cs_element_layout_cell _id=”35″ ][cs_element_headline _id=”36″ ][cs_content_seo]How we do it\n\n[/cs_content_seo][cs_element_text _id=”37″ ][cs_content_seo]In comparison, Codasip Studio generates all the needed tools and code from the CodAL description fully automatically. All the generated parts are new and natively aware of the custom instructions. We don’t use intrinsics, and are thus able to compile better performing code.\n\n[/cs_content_seo][cs_element_image _id=”38″ ][/cs_element_layout_cell][/cs_element_layout_grid][cs_element_layout_grid _id=”39″ ][cs_element_layout_cell _id=”40″ ][cs_element_text _id=”41″ ][cs_content_seo]Codasip offers off-the-shelf RISC-V processor cores which are licensed in the usual way with RTL, a testbench and SDK. These cores can also be licensed in the CodAL source code which was used to design the cores and to generate the SDK and HDK. The CodAL source can be edited to create custom extensions and to modify other architectural features.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”42″ ][cs_element_button _id=”43″ ][cs_content_seo]Discover the Codasip Studio toolset\n\n[/cs_content_seo][cs_element_button _id=”44″ ][cs_content_seo]Discover Codasip RISC-V Processors\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”45″ ][cs_element_layout_grid _id=”46″ ][cs_element_layout_cell _id=”47″ ][cs_element_text _id=”48″ ][cs_content_seo]Microsemi used Codasip Studio on an audio design where they were seeking to replace a proprietary embedded core with a RISC-V one. They started with the base 32-bit instruction set but found that the cycle count was far too high. Adding the multiplication instructions improved performance but did not achieve their requirements. Finally, they worked with Codasip to create custom DSP extensions that significantly improved the performance 56× with processor core gatecount growing by 2.4×.
Not only did they achieve their performance goal but their codesize reduced from 232 kB to 64 kB reducing the required instruction memory area by 3.6×.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”49″ ][cs_element_image _id=”50″ ][cs_element_text _id=”51″ ][cs_content_seo]The Microsemi case: Reducing cycle count with custom RISC-V extensions. Source: Codasip.\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”52″ ][cs_element_text _id=”53″ ][cs_content_seo]Customer Use Case
Microsemi\n\n[/cs_content_seo][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][cs_element_section _id=”54″ ][cs_element_layout_grid _id=”55″ ][cs_element_layout_cell _id=”56″ ][cs_element_headline _id=”57″ ][cs_content_seo]Contact Us\n\n[/cs_content_seo][/cs_element_layout_cell][cs_element_layout_cell _id=”58″ ][contact-form-7 id=”8420″ title=”GENERAL”][/cs_element_layout_cell][/cs_element_layout_grid][/cs_element_section][/cs_content]