Meet us at the RISC-V Summit in San Jose, CA, on December 13-14, 2022! 

Codasip Announces Bk5-64, a New 64-bit RISC-V Processor


November 28, 2017

Brno, Czech Republic – November 28th, 2017 – Codasip, the leading supplier of RISC-V® embedded processor IP, today announced that it has expanded its Berkelium processor portfolio to include the Bk5-64, its first implementation of the 64-bit RISC-V ISA.

Codasip now offers customers the broadest selection of RISC-V processors in the market, spanning from the ultra-low-power zero-stage Bk1 to the high-data-bandwidth, energy-efficient Bk5-64. All Berkelium processors are generated via the unique Codasip Studio customization tool, allowing for fast configuration and optimization of the cores.

With the rapid expansion of data-intensive applications such as storage and wireless networking, the market is asking for embedded processor solutions with the right balance of performance and energy efficiency that 64-bit computing requires,” stated Karel Masařík, founder and CEO of Codasip. “By introducing the Bk5-64, Codasip is addressing the need for affordable 64-bit embedded processors, complete with a state-of-the-art LLVM-based software development toolchain with advanced profiling.”

RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.

Said Rick O’Connor, Executive Director of the non-profit RISC-V Foundation, “Today’s announcement from Codasip shows continued growth of the RISC-V architecture and the industry’s need for a new open, free ISA. We look forward to seeing more developments from Codasip and others from the RISC-V ecosystem in the future.

The Berkelium Bk5-64 RISC-V processor is available later in Q4 of 2017.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of the RISC-V open-standard ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

Kava

Related Posts

Check out the latest news, posts, papers, videos, and more!

How to reduce the risk when making the shift to RISC-V

November 17, 2022
By Lauranne Choquin

DAC 2022 – Is it too risky not to adopt RISC-V?

July 18, 2022
By Brett Cline

Processor design automation to drive innovation and foster differentiation

July 7, 2022
By Lauranne Choquin

Rambus Selects Codasip Studio for SDK Development of RISC-V Processor


November 14, 2017

Codasip Studio Enables Fully Automated Development of the Processor Software Design Kit While Saving Significant Time and Resources

Brno, Czech Republic – November 14th 2017 – Codasip, Ltd., the leader in RISC-V embedded processor IP cores, today announced that Rambus selected Codasip Studio for developing its next-generation RISC-V security products. Codasip Studio provides fully automated generation of the Software Design Kit (SDK) for RISC-V processors. Codasip Studio utilizes a high-level design flow based on a proprietary modeling language called CodAL that significantly reduces the amount of engineering time and resources required to create, verify, and validate SDKs for embedded processors.

“Security is the leading issue for IoT, automotive and other fast-growing markets, and it is critical for Rambus to deliver superior products to market in a timely fashion,” said Bret Sewell, SVP and general manager of the Rambus Security Division. “We selected Codasip Studio as a high-level design tool for SDK generation because it allows for fast design space exploration, and because of the high quality of results we are realizing in the automatically generated compiler toolchain.”

Rambus Security is a leading provider of IP cores, software and services, dedicated to delivering a secure foundation for a connected world. Their embedded security solutions are designed to address the worldwide threat to data integrity as more devices are connected to the cloud. Rambus foundational technologies protect nearly nine billion licensed products annually, providing secure access to data and creating an economy of digital trust between our customers and their customer base. Additional information is available at rambus.com/security.

Unmatched Automation and Efficiency

The high degree of automation provided by Codasip Studio makes it easy to make use of the power of embedded processor design techniques. Tasks that traditionally take weeks or months, tying up specialized and expensive resources, are highly automated and can be completed in days, significantly reducing both design time and cost.

Unified Development Model

Capabilities of the RISC-V embedded processor only need to be described once in the CodAL high-level language, and from this single description, everything needed to design, integrate, and program the embedded processor is automatically derived. This eliminates the need to express the same functionality in multiple task dependent formats, and traditional manual tasks.

In addition to its processor design capabilities, Codasip Studio includes powerful debugging and profiling – which makes even the most complex embedded processor designs easy to manage.

Key features of Codasip Studio include:

  • Powerful Eclipse-based IDE
  • Support for leading open source tools and standards
  • Algorithm to implementation design flow
  • Automatic generation of complete ASIP toolchain
  • Advanced profiling tools
  • End-to-end multiprocessor-aware debug
  • Multi-core SDK management

“Codasip enables companies like Rambus to meet the demanding time-to-market requirements for security products by providing the unique automation of our Studio toolset,” said Karel Masařík, co-founder and CEO of Codasip. “Having selected Codasip Studio for their security products, Rambus can eliminate the burden of internally developing and maintaining a software toolchain, and focus their software resources instead on bringing high-quality products to market.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of an open standard such as the RISC-V ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V foundation (riscv.org) and long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. More information on Codasip’s products and services is available at codasip.com.

Press Contact:
Chris Jones, VP of Marketing
Codasip Ltd.
jones@codasip.com
(408) 857-3236

Kava

Related Posts

Check out the latest news, posts, papers, videos, and more!

How to reduce the risk when making the shift to RISC-V

November 17, 2022
By Lauranne Choquin

DAC 2022 – Is it too risky not to adopt RISC-V?

July 18, 2022
By Brett Cline

Processor design automation to drive innovation and foster differentiation

July 7, 2022
By Lauranne Choquin

Codasip and Avery Partner to Improve Regression Test Methodology of RISC-V Processors


November 8, 2017

Brno, Czech Republic – November 8th 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced its partnership with Avery Design Systems, the provider of cutting-edge verification intellectual property (VIP) solutions for SoC and IP companies.

Codasip develops licensable RISC-V processors, the Berkelium (Bk) series, via a unique customization tool called Codasip Studio, allowing for fast configuration and optimization of the cores. Studio enables practically an endless number of RISC-V variants, which places extensive demands on verification.

“With the flexibility of Codasip Studio, extensive verification becomes essential, and we are constantly on the lookout for innovative VIP solutions that will make a part of the verification process faster, easier, or more reliable,” says Marcela Zachariášová, the VP of Verification at Codasip. “Avery Design Systems offer some very useful features.”

Specifically, Codasip employs the Avery VIP fault injection feature, which introduces random or precisely-planned faults into the communication lines between the processor and the surrounding components. This allows simulation of unexpected corner cases. Such stress testing is vital to ensure that the processors are robust and reliable even when faults occur.

“We need to ensure that all variants of our RISC-V processors handle error scenarios correctly and can respond to any type of error from the surrounding components without crashing or freezing. Avery’s fault injection helps us analyze such scenarios in our cores,” explains Mrs. Zachariášová.

Codasip itself, and with assistance of industry alliances, has introduced innovations in the field of verification, achieving best-in-class results in verification automation and acceleration. The recent introduction of Avery’s fault injection technology has helped to further improve Codasip’s regression methodology.

“We have partnered with Avery because of unique benefits their fault injection technology brings,” concludes Mrs. Zachariášová.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of an open standard, such as the RISC-V ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU based processor solutions, Codasip is committed to open standards for embedded processors.

Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

About Avery

Founded in 1999, Avery Design Systems, Inc. enables system and SoC design teams to achieve dramatic functional verification productivity improvements through formal analysis applications for RTL and gate-level X verification, and robust verification IPs for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, Unipro, CSI/DSI, Soundwire, and CAN FD standards.

Avery is headquartered in Tewksbury, Massachusetts, and operates an R&D center in Taipei, Taiwan. Avery’s products are directly marketed and distributed in the US, Europe, Japan, Korea, and Taiwan.

For further information about Avery Design Systems, visit www.avery-design.com.

Kava

Related Posts

Check out the latest news, posts, papers, videos, and more!

How to reduce the risk when making the shift to RISC-V

November 17, 2022
By Lauranne Choquin

DAC 2022 – Is it too risky not to adopt RISC-V?

July 18, 2022
By Brett Cline

Processor design automation to drive innovation and foster differentiation

July 7, 2022
By Lauranne Choquin

Codasip Announces Latest RISC-V Processor


August 21, 2017

The Newest Codasip RISC-V Processor is Ideal for IoT Designs

Brno, Czech Republic – August 21st 2017 – Codasip, the leading supplier of RISC-V® embedded CPU cores, today announced the newest addition to their Berkelium (Bk) family of RISC-V processors. The Codasip Bk-1 processor is an FSM processor targeted at the Internet of Things (IoT) by offering ultra-low power, the lowest cost of all comparable embedded processors, and optimal performance/power efficiency.

Karel Masařík, CEO and founder of Codasip, stated: “This processor is perfect for IoT ASIC designers looking to move up from 8-bit processors to 32-bit processors. Like all members of the Codasip Bk family of processors, the Bk-1 is fully compliant with the RISC-V open standard, assuring customers that their embedded software is truly portable and their designs are not locked into a proprietary instruction set architecture (ISA) such as Arm.”

The Bk-1 processor was designed to provide impressive 32-bit performance, small code size, and minimal power, area, and cost. In its basic configuration, the Bk-1 starts at 9k gates while delivering a maximum clock frequency of up to 350 MHz in a 55nm process. The Bk-1 has an optional power management unit, JTAG debug controller, and bridges to the AMBA buses so it can be easily integrated into existing Arm designs.

Codasip provides their customers with high-level design tools that automatically profile the embedded SW and allow ASIC designers to tailor the Bk-1 processor exactly to its intended application. This unique ability to automatically modify the Codasip cores results in far better implementations compared to other processor IP vendors, and allows for the process to be easily completed in a day or two with the silicon proven Codasip Studio tool suite.

“Codasip’s new Bk-1 processor is another great milestone for the RISC-V ecosystem and shows ongoing market growth of its open and free architecture,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “The Foundation will continue to support member organizations, such as Codasip, in bringing to market RISC-V-based processors that enable new designs and innovation.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of an open standard, such as the RISC-V ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V foundation (riscv.org) and a long-term supplier of LLVM and GNU based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. More information on Codasip’s products and services is available at codasip.com.

Press Contact

Codasip North America
Dan Ganousis
ganousis@codasip.com
+1 (303) 859-3048

Codasip EMEA
Roddy Urquhart
urquhart@codasip.com
+44 753 158 7023

Kava

Related Posts

Check out the latest news, posts, papers, videos, and more!

How to reduce the risk when making the shift to RISC-V

November 17, 2022
By Lauranne Choquin

DAC 2022 – Is it too risky not to adopt RISC-V?

July 18, 2022
By Brett Cline

Processor design automation to drive innovation and foster differentiation

July 7, 2022
By Lauranne Choquin