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Why and How to Customize a Processor


October 1, 2021

Processor customization is one approach to optimizing a processor IP core to handle a specific workload. The idea is to take an existing core that could partially meet your requirements and use it as a starting point for your optimized processor. Now, why and how to customize a processor?

Why you should consider creating a custom core?

Before we start, let’s make sure we are all on the same page. Processor configuration and processor customization are two different things. Configuring a processor means setting the options made available by your IP vendor (cache size, MMU support, etc.). Customizing a processor means adding or changing something that requires more invasive changes such as changing the ISA, writing new instructions. In this blog post we focus on processor customization.

Customizing an existing processor is particularly relevant when you create a product that must be performant, area efficient, and energy efficient at the same time. Whether you are designing a processor for an autonomous vehicle that requires both vector instructions and low-power features, or a processor for computational storage with real-time requirements and power and area constraints, you need an optimized and specialized core.

Processor customization allows you to bring in a single processor IP all the architecture extensions you need, standard or custom, that would have been available in either multiple IPs on the SoC or in one big, energy intensive IP. Optimizing an existing processor for your unique needs has significant advantages:

  • It allows you to save area and optimize power and performance as it targets exactly what you need.
  • It is ready to use. The processor design has already been verified – you only have to verify your custom extensions.
  • You design for differentiation. Owning the changes, you create a unique product.

Now, one may think that this is not so easy. How reliable is the verification of a custom processor? Differentiation is becoming more difficult, time consuming, and sometimes more expensive. The success of processor customization relies on two things:

  • An open-source ISA such as RISC-V.
  • Design and verification automation.

Custom processor, ASIP, Domain-Specific Accelerator, Hardware Accelerator, Application-Specific processor… are all terms related to processor customization.

Customizing a RISC-V processor

Remember: the RISC-V Instruction Set Architecture (ISA) was created with customization in mind. If you want to create a custom processor, starting from an existing RISC-V processor is ideal.

You can add optional standard extensions and non-standard custom extensions on top of the base instruction set to tailor your processor for a given application.

RISC-V Modular Instruction Set. Source: Codasip.

For a robust customization process that ensures quality in the design and confidence in the verification, automation is key.
With Codasip you can license RISC-V processors:

  • In the usual way (RTL, testbench, SDK).
  • In the CodAL source code.

CodAL is used to design Codasip RISC-V processors and generate the SDK and HDK. You can then edit the CodAL source code to create your own custom extensions and modify other architectural features as needed.

Microsemi opted for this approach as they wanted to replace a proprietary embedded core with a RISC-V one. Check this great processor customization use case with Codasip IP and technology!

Processor design automation with Codasip Studio

The legacy approach to adding new instructions to a core is based on manual editing. Adding custom instructions must be reflected in the following areas:

  • Software toolchain.
  • Instruction set simulator.
  • Verification environment.
  • RTL.
Design Automation without Codasip Studio. Source: Codasip.

With the software toolchain, intrinsics can be created so that the new instructions are used by the compiler, but this also means that the application code needs updating. However, modifying the existing ISS and RTL are both potential sources of errors. Lastly, if the verification environment needs changing, this is a further area for problems. Verifying these manual changes is a big challenge and adds risk to the design project.

Some vendors offer partially automated solutions, but by not covering all aspects of processor customization they still leave room for error due to the manual changes.

Design Automation with Codasip Studio. Source: Codasip.

In contrast, with Codasip the changes are only made to the CodAL source code. The LLVM toolchain is automatically generated with support for the new instructions. Similarly, the ISS and RTL are generated to include the custom instructions and can be checked using the updated UVM environment. This approach not only saves time, but is a more robust customization process.

Create an application-specific processor with RISC-V and Codasip

As differentiation is becoming more difficult, time consuming and sometimes more expensive with traditional processor design, customizing a processor so that it will meet your unique requirements is the key. Creating an application-specific processor efficiently, without compromising PPA, requires an open-source architecture and tools to automate the design and verification process. Find out more in our white paper on “Creating Domain-Specific Processors using custom RISC-V ISA instructions”.

Roddy Urquhart

Roddy Urquhart

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What is needed to support an operating system?


October 15, 2020

For each embedded product, software developers need to consider whether they need an operating system; and if so, what type of embedded OS. Operating systems vary considerably, from real-time operating systems with a very small memory footprint to general-purpose OSes such as Linux with a rich set of features.

Which type of OS is typically found on an embedded system?

Choosing a proper type of operating system for your product – and consequently working out the required features of the embedded processor – depends significantly on whether you face a hard real-time requirement. Safety-critical and industrial systems such as an anti-lock braking system or motor control will have hard maximum response times. At the other end of the spectrum, consumer systems such as audio or gaming devices may be able to tolerate buffering, as long as the average performance is adequate. Such systems are said to have soft real-time requirements.

Bare metal

A hard real-time requirement can be achieved by writing so-called bare-metal software that directly controls the underlying hardware. Bare-metal programming is typically used when the processor resources are very limited, the software is simple enough, and/or the real-time requirements are so tight that introduction of a further abstraction layer would complicate meeting these hard real-time requirements. The disadvantage to this approach is that such bare-metal software needs to be written as a single task (plus interrupt routines), making it difficult for programmers to maintain the software as its complexity grows.

Real-time Operating Systems

When dealing with more complex embedded software, it is often advantageous to employ a Real-Time Operating System (RTOS). It allows the programmer to split the embedded software into multiple threads whose execution is managed by the small, low-overhead “kernel” of the RTOS. The use of the multi-threaded paradigm enables developers to create and maintain more complex software while still allowing for sufficient reactivity.

RTOSes typically operate with a concept of “priority” assigned to individual threads. The RTOS can then “pre-empt” (temporarily halt) lower-priority threads in favour of those with higher priority, so that the required real-time constraints can be met. The use of an RTOS often becomes necessary when adopting complex libraries or protocol stacks (such as TCP/IP or Bluetooth) as this third-party software normally consists of multiple threads already.

The embedded processor requirements of a simple RTOS, such as FreeRTOS or Zephyr, are truly modest. It is sufficient to have a RISC-V processor with just machine mode (M) and a timer peripheral. However, rigorous software development is needed as machine mode offers unconstrained access to all memory and peripherals with associated risks. Extra protection is possible through a specialized RTOS such as those developed for functional safety, like SAFERTOS, or for security.

If a processor core supports both machine (M) and user (U) privilege modes and has physical memory protection (PMP), it is possible to establish separation between trusted code (with unconstrained access) and other application code. With PMP, the trusted code sets up rules for each portion of the application code, saying which parts of memory (or peripherals) it is allowed to access. PMP can for instance be used to prevent third-party code from interfering with the data of the rest of the application, or to detect stack overflows. Employing PMP therefore increases the safety and security of a system, but at the cost of additional hardware required for its support.

We also discuss embedded OS support in this video!

Rich operating systems

For applications requiring a more advanced user interface, sophisticated I/O and networking, such as in set-top boxes or entertainment systems, an RTOS is likely to be too simplistic. The same applies if there are complex computations, requirements for a full process isolation and multitasking, filesystem & storage support, or a full separation of application code from hardware via device drivers. Systems like these generally have soft real-time requirements and can be best served by a general-purpose rich operating system such as Linux. As mentioned in our blog post dedicated to processor complexity, Linux requires multiple RISC-V privilege modes – machine, supervisor, and user modes (M, S, U) – as well as a memory management unit (MMU) for virtual-to-physical address translation. Also, the memory footprint of such a system is significantly larger compared to a simple RTOS.

Finally, for embedded systems that require both hard real-time responses and features of a rich OS like Linux, it is common to design them with two communicating processor subsystems, one supporting an RTOS and the other running Linux.

The OS support will impact your processor choice

Choosing the appropriate embedded OS for your product and identifying the features required for your embedded processor depends heavily on the type of real-time requirements you face. Together with processor performance and complexity, among other key considerations, the OS support you need should be taken into account when choosing a processor. To find out more, read our white paper on “What you should consider when choosing a processor IP core”.

Roddy Urquhart

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What is processor core complexity?


September 10, 2020

The more complex a processor core, the larger the area and power consumption. But increasing complexity is not a single dimension as processors can be more complex in different ways. In selecting a processor IP core, it is important to choose the right sort of processor complexity for your project.

What defines the complexity of a processor?

There are different ways of thinking about processor complexity. Word length, execution units, privilege modes, virtual memory and security features are important considerations that will make your processor core more complex. It is important to understand what you really need for your project.

Word length

Generally, the smaller the word length, the smaller the core and the lower the power, however this is not always the case. An 8-bit core, such as the 8051, is comparable in gate count to the smallest 32-bit cores, but power consumption is usually worse. An 8-bit core requires more memory accesses due to less computation per clock cycle requiring more cycles. The net impact is that it requires more power to complete a computation.

Execution units

Processor cores vary considerably in the complexity of their execution units. The simplest are basic single ALUs requiring many common operations to be implemented by the simple instructions – for example using shift and add to implement a multiplication. It is therefore commonplace for cores to have a hardware multiplier and divider. In the event of needing good floating-point performance, adding a hardware Floating Point Unit (FPU) will provide significantly better performance. This option is available for Codasip’s Low-Power (L) and High-Performance (H) Embedded RISC-V processor cores but at the price of roughly doubling the core size.

Superscalar architectures with instruction-level parallelism

So far, we have assumed a single computational thread and scalar processing units which execute one instruction at a time. Superscalar architectures have instruction-level parallelism able to fetch multiple instructions and dispatch them to different execution units. A dual-issue core processing one thread can theoretically have up to double the performance of a single-issue core. However, a thread can stall making both execution units temporarily inactive. If there are two hardware threads (harts), then if one thread stalls, the other can continue execution.

Processors can vary considerably in pipeline depth and there is a direct relationship between this depth and latency. Some applications can tolerate high latency, with the consequence being slower response to interrupts, in return for high clock frequencies and throughput. Other applications require rapid responses to interrupts so need shorter pipelines.

We also discuss processor complexity in this video!

Privilege modes

Another area of complexity is privilege modes. The more modes, the more complex the core logic. Many embedded applications run in machine mode, which means that the code has full access to the core – like root privilege in Linux. Such code must be completely trusted to avoid negative consequences. In more sophisticated applications, a range of privileges such as machine, supervisor and user may be offered. Normal applications will run in user mode with the greatest amount of protection and some software requiring greater privilege will use supervisor mode.

Virtual memory

Virtual memory also requires additional processor resources such as a memory management unit (MMU) and translation lookaside buffer (TLB) to handle translating virtual memory addresses to physical addresses. This brings additional costs in terms of area and power dissipation without improving processor throughput. Nevertheless, virtual memory is necessary for using rich operating systems such as Linux which enable more complex software to be used.

So, when choosing a processor core, work out what sort of execution units, memory management, privilege and security you need. That combination will determine the complexity of the core.

Consider processor complexity when choosing a core – but not only that!

So, when choosing a processor core, work out what sort of execution units, memory management, privilege and security you need. That combination will determine the complexity of the core. But that’s not all. If PPA numbers are typically considered when looking at the wide choice of processor IP cores on the market, that’s not enough. Processor complexity is one element, but processor performance, software requirements and the ISA, among others, are key considerations to investigate. We cover these in our white paper “What you should consider when choosing a processor IP core”.

Roddy Urquhart

Roddy Urquhart

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Understanding the Performance of Processor IP Cores


August 20, 2020

Looking at any processor IP, you will find that their vendors emphasize PPA (performance, power & area) numbers. In theory, they should provide a level playing field for comparing different processor IP cores, but in reality, the situation is more complex. Let us consider processor performance.

What does processor performance mean?

The first thing to think about is what aspect of performance you care about. Do you care more about the absolute throughput that you want (performance per second), or the performance per MHz? In an application such as machine vision, which is continuously running and requiring the use of complex algorithms, it is likely that you will care about the absolute throughput. However, if you have a wireless sensor node with a low duty cycle, when the node wakes up, you will want it to be active for as few clock cycles as possible. This means you will care about how much computation you achieve per MHz.

About 40 years ago, computers were compared on the basis of MIPS (millions of instructions per second) although the problem is – what is an instruction? Instructions vary considerably in complexity and from one architecture to another, thus an operation will generally require less cycles in a CISC processor than a RISC one. MIPS were only helpful when comparing products with similar architectures and were called “meaningless indices of performance” by some!

Another thing to think about is the type of computation that you expect to care most about. Is it integer operations – and if so, which ones – or, say, floating-point computations? In the past, MFLOPS (million floating point operations per second) was a popular measure. But again, what is an ‘operation’?

Popular synthetic benchmarks

Today, synthetic benchmarks are universally used with processor IP cores. They have the following characteristics:

  • They are relatively small and portable.
  • They are representative of commonly used relevant applications.
  • They are reproducible and transparent.
  • They can be applied to a range of processors fairly.
  • They express the benchmark result as a single number.

Dhrystone

A benchmark that has been popular for the last 36 years is the Dhrystone benchmark. Its name is a play on words comparing it with the once-popular Whetstone benchmark. While Whetstone focused on floating point operations, Dhrystone focused on integer and string operations. The Dhrystone benchmark results are generally quoted as DMIPS (the Dhrystone score divided by that of a nominally 1 MIPS machine). The benchmark has been criticized because modern compilers can optimize away parts of the work, meaning that it partly tests compiler rather than processor performance.

For floating point, Whetstone is rarely used at present and it is more likely that LINPACK would be used. LINPACK involves LU decomposition of a matrix using floating point numbers. The result is expressed in MFLOPS.

CoreMark

Another popular synthetic benchmark for embedded applications has been EEMBC’s CoreMark® which aims to undertake operations that are representative of embedded integer processing needs. These include list processing, matrix operations, finite state machines, and CRC.

Find more details and some tips to measure processor performance according to your needs in this video!

Assessing performance when choosing a processor

There are various benchmark systems out there, each suited for measuring a slightly different type of performance. So how do you assess performance when choosing processor IP for your project?

If your embedded software has similar operations to a synthetic benchmark, then that benchmark may give you useful initial guidance quickly and simply. However, normally such benchmarks are quoted per MHz, for example CoreMark/MHz. The per MHz figure is normally a good indication for a low-power application where you are looking for good results per cycle. However, if you are looking for high absolute performance, this may be misleading. Instead you should consider, say, the CoreMarks achievable at your target clock frequency.

If your main issue is floating-point performance, bear in mind that DMIPS and CoreMark are integer benchmarks. You would be better comparing cores on the basis of a floating-point benchmark such as LINPACK.

Ultimately, it always makes sense to invest the time in running realistic software on a processor core to assess whether the core gives you the performance you need. If you are looking at RISC-V, then profiling your software to understand where the computational bottlenecks are can also lead to assessing whether adding custom instructions can give you improvements in performance.

It is not just about processor performance and scores

In this article we have looked at processor performance, but that is only one aspect of PPA and one factor to consider when choosing a processor. PPA numbers are always about balance and all of them matter when choosing an IP for a project, among other key considerations. The ISA, processor complexity, processor memory or even the licensing model will impact your choice. Find out more in our white paper “What you should consider when choosing a processor IP core“.

Roddy Urquhart

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Codasip Expands its Global Reach by Signing Channel Partnerships throughout Asia


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed new reseller representative agreements with leading firms in China, Taiwan, Japan, and India.

New strategic partnerships were formed with Shanghai Jiatao, Maojet Technologies of Taiwan, Delphinium Technologies of Bengaluru, India, and Japan Marketing Office to assist Codasip in reaching the rapidly expanding Asia markets.

“Adding these great companies to our partner roster demonstrates our commitment to making Codasip the premier provider of RISC-V processors,” stated Karel Masařík, founder and CEO of Codasip. “RISC-V momentum is growing and we are uniquely positioned for success with a global presence and a strategy of delivering configurable RISC‑V-based products and development tools.”

Codasip aims to have the most comprehensive portfolio of RISC‑V processor IP in the industry, which is achieved by employing the Codasip Studio processor development tools to continually bring new cores to market. The unique toolset also helps customers differentiate their products by automatically tailoring their processor IP to design and software requirements – and it does so with less cost and risk than with using general-purpose components.

Studio dramatically simplifies the process of tailoring a processor solution and delivering potentially enormous performance improvements.  Further, end users can exploit the power of Studio themselves to build their own unique RISC-V processor that is just right for their application.

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.

For more information about Codasip’s products and services, visit codasip.com.

Kava

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Codasip Inks Deal with Delphinium Technologies to Establish India Presence


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed a representative agreement with Delphinium Technologies to establish Codasip’s presence in India.

Delphinium Technologies of Bengaluru, India, is focused on bringing state-of-the-art EDA technologies and IP to the electronics engineering world.

“Indian companies, government-backed research facilities and universities are all heavily invested in the RISC‑V movement,” stated Susheel Kumar, founder and director of Delphinium.  “Codasip’s technology can help these enterprises become more productive as they develop innovative RISC‑V derivatives. We look forward to helping Codasip introduce their RISC-V processors, tools, and design methodology to the India design community.”

India represents a new frontier for processor IP companies like Codasip,” stated Jerry Ardizzone, Vice President of Worldwide Sales at Codasip. “We are uniquely positioned with our configurable RISC‑V-based products and development tools to help jumpstart the growing India processor and semiconductor design communities, and we look to Delphinium to help us establish roots in the market there.”

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.
For more information about Codasip’s products and services, visit codasip.com.

About Delphinium

For more information about Delphinium, visit www.delphiniumtech.com.

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Maojet and Codasip Join Forces to Deliver RISC-V Processors to Taiwan


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has signed a representative agreement with Maojet Technology Corporation, making them Codasip’s exclusive sales partner in Taiwan.

Maojet is the leading EDA tool and IP distributor in Taiwan, established in 1992 and having since built a comprehensive portfolio of EDA tools from system level to RTL, manufacturing and PCB, in addition to a large family of silicon-proven SoC IP solutions.

“We are witnessing growing RISC-V momentum in Taiwan, as our customers are always looking for new and innovative IP,” said Ted Tsai, General Manager of Maojet.  “The combination of Codasip’s RISC‑V processors and processor development tools is unique to the industry, and exactly what our customers need to differentiate in the highly competitive semiconductor market. We anticipate a long and successful partnership with Codasip.”

Taiwan is home to some of the world’s most innovative semiconductor companies and represents a huge opportunity for Codasip technology,” stated Jerry Ardizzone, Vice President of Worldwide Sales at Codasip. “Together, Maojet and Codasip will work to bring the best in RISC‑V technology to these companies and support them in reaching their fullest potential.”

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.
For more information about Codasip’s products and services, visit codasip.com.

About Maojet

For more information about Maojet, visit www.maojet.com.tw.

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Codasip Partners with Shanghai Jiatao to Bring Configurable RISC-V Processors to China Market


September 10, 2018

Campbell, California – September 10th 2018 – Codasip, the leading supplier of RISC‑V® embedded processor IP, today announced that it has entered into a partnership with Shanghai Jiatao Industrial Company, making them an authorized reseller of Codasip products throughout China.

Jiatao was founded in 2009 to focus on the introduction and promotion of high-value and differentiated semiconductor IP to China. Additionally, they are the strategic partner of Design and Reuse (www.design-reuse.com) for China, and have co-organized IP SoC Days in China since 2010.

“We are very excited to add Codasip technology to the Jiatao product family,” said Mark Ma, founder and president of Jiatao.  “Codasip’s portfolio of RISC‑V processors and processor development tools are very much in demand in China, and we look forward to working with them to grow their presence here.”

We are experiencing a huge demand for our Berkelium series of RISC‑V processors in China, and Jiatao helps us reach customers quickly and effectively,” stated Jerry Ardizzone, Vice President of Worldwide Sales at Codasip. “Mark and his team are well-established professionals in the China semiconductor industry and provide outstanding customer support.”

About RISC-V

RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration. Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.
For more information, visit www.riscv.org.

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools, providing ASIC designers with all the advantages of the RISC-V open ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V Foundation and a long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel.
For more information about Codasip’s products and services, visit codasip.com.

About Jiatao

For more information about Jiatao, contact them at info@jiataochina.com.

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Rambus Selects Codasip Studio for SDK Development of RISC-V Processor


November 14, 2017

Codasip Studio Enables Fully Automated Development of the Processor Software Design Kit While Saving Significant Time and Resources

Brno, Czech Republic – November 14th 2017 – Codasip, Ltd., the leader in RISC-V embedded processor IP cores, today announced that Rambus selected Codasip Studio for developing its next-generation RISC-V security products. Codasip Studio provides fully automated generation of the Software Design Kit (SDK) for RISC-V processors. Codasip Studio utilizes a high-level design flow based on a proprietary modeling language called CodAL that significantly reduces the amount of engineering time and resources required to create, verify, and validate SDKs for embedded processors.

“Security is the leading issue for IoT, automotive and other fast-growing markets, and it is critical for Rambus to deliver superior products to market in a timely fashion,” said Bret Sewell, SVP and general manager of the Rambus Security Division. “We selected Codasip Studio as a high-level design tool for SDK generation because it allows for fast design space exploration, and because of the high quality of results we are realizing in the automatically generated compiler toolchain.”

Rambus Security is a leading provider of IP cores, software and services, dedicated to delivering a secure foundation for a connected world. Their embedded security solutions are designed to address the worldwide threat to data integrity as more devices are connected to the cloud. Rambus foundational technologies protect nearly nine billion licensed products annually, providing secure access to data and creating an economy of digital trust between our customers and their customer base. Additional information is available at rambus.com/security.

Unmatched Automation and Efficiency

The high degree of automation provided by Codasip Studio makes it easy to make use of the power of embedded processor design techniques. Tasks that traditionally take weeks or months, tying up specialized and expensive resources, are highly automated and can be completed in days, significantly reducing both design time and cost.

Unified Development Model

Capabilities of the RISC-V embedded processor only need to be described once in the CodAL high-level language, and from this single description, everything needed to design, integrate, and program the embedded processor is automatically derived. This eliminates the need to express the same functionality in multiple task dependent formats, and traditional manual tasks.

In addition to its processor design capabilities, Codasip Studio includes powerful debugging and profiling – which makes even the most complex embedded processor designs easy to manage.

Key features of Codasip Studio include:

  • Powerful Eclipse-based IDE
  • Support for leading open source tools and standards
  • Algorithm to implementation design flow
  • Automatic generation of complete ASIP toolchain
  • Advanced profiling tools
  • End-to-end multiprocessor-aware debug
  • Multi-core SDK management

“Codasip enables companies like Rambus to meet the demanding time-to-market requirements for security products by providing the unique automation of our Studio toolset,” said Karel Masařík, co-founder and CEO of Codasip. “Having selected Codasip Studio for their security products, Rambus can eliminate the burden of internally developing and maintaining a software toolchain, and focus their software resources instead on bringing high-quality products to market.”

About Codasip

Codasip delivers leading-edge processor IP and high-level design tools that provide ASIC designers with all the advantages of an open standard such as the RISC-V ISA, along with the unique ability to automatically optimize the processor IP. As a founding member of the RISC-V foundation (riscv.org) and long-term supplier of LLVM and GNU-based processor solutions, Codasip is committed to open standards for embedded processors. Formed in 2006 and headquartered in Brno, Czech Republic, Codasip currently has offices in the US and Europe, with representatives in Asia and Israel. More information on Codasip’s products and services is available at codasip.com.

Press Contact:
Chris Jones, VP of Marketing
Codasip Ltd.
jones@codasip.com
(408) 857-3236

Kava

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