RISC-V Summit US 2023: CHERI in full bloom!
RISC-V Summit US 2023 did not disappoint. With more than 1,000 attendees over 3 days, our team was full on. After announcing our 700 family and the first ever commercial implementation of CHERI a couple of weeks before the event, we were prepared for what was, we believe, the best RISC-V event we’ve ever attended. […]
Codasip 700 RISC-V processor family: Bringing the world of Custom Compute to everyone
Today, technology innovators must have new ways to create differentiated products. How are they supposed to meet the demand for more computational performance when semiconductor scaling laws are showing their limits? There is only one way: having a compute that is custom for specific needs. And what do we need for that? Several aspects: Architecture optimization, […]
How the SYCLOPS project democratizes AI acceleration
Codasip Labs is all about innovation, and specifically the commercialization of that innovation. Naturally, with the rise of Artificial Intelligence (AI) and Machine Learning (ML), these areas have become a key focus for us. At the beginning of 2023, we joined the New Horizon Europe Project SYCLOPS (Scaling extreme analYtics with Cross-architecture acceLeration based on […]
RISC-V customization gets a standing ovation – no fragmentation drama!
Uniting diversity and compatibility Processor vendors have always tried to create a large software ecosystem around their products, because it creates stickiness and it naturally “locks-in” large numbers of customers who have invested in the creation of dedicated software. This effect is growing over time as the quantity of software is ever increasing per product: […]
It’s all about RISC-V code size
Here at Codasip we’re passionate about reducing the code size of our RISC-V cores for our customers, but why? Are we not making the core larger and more complex as we add instructions to improve the situation? In short the answer is yes we are, any instructions added to the processor increase the size, complexity, […]
Increasing design skills for custom compute
As discussed in an another blog post by Mike Eftimakis, there are limitations to traditional design methods that use “off-the-shelf” processor cores. Traditionally, software engineers try to fit their code to the constraints of the chosen processor hardware. The alternative is to co-optimize the hardware and software together to create a custom compute solution. You […]
Developing a customized RISC-V core for MEMS sensors
We recently described how Codasip Labs is working with the NimbleAI project to push the boundaries of neuromorphic vision. Let’s talk about another cool project. This project is focused on another sense, hearing. We will use our unique Codasip Studio design toolset to develop a customized RISC-V core for MEMS (micro-electro-mechanical system) sensors. Again, technology […]
When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovation
Alright, let’s talk about Barcelona. Now, you might be thinking of mouthwatering tapas, smooth local wines, and the pulsing life in every corner of the city. It’s a foodie’s paradise for sure—and I took full advantage— but last week, Barcelona became a playground for tech enthusiasts too. The reason? The first-ever RISC-V Summit Europe. RISC-V […]
No one-size-fits-all approach to RISC-V processor optimization
As the demand for high-performance processors continues to grow and semiconductor scaling laws continue to show their limits, the need for processor optimization is inevitable. As I explained in a previous blog, RISC-V is designed to enable this. However, there is no one-size-fits-all approach to processor optimization. As each workload and each application will have […]