How to reduce the risk when making the shift to RISC-VIn conversation with Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip
November 17, 2022
November 17, 2022
With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program.
We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about this.
On the left: Rupert Baines – CMO at Codasip; on the right: Vijay Krishnan – GM, RISC-V Ventures, Incubation and Disruptive Innovation (IDI) Group at Intel Corporation
There is real risk and then there is perceived risk. Regarding the former, any architectural transition adds complexity, but with RISC-V the entire hardware and software ecosystem is coming together in a manner which minimizes the real risk, while unleashing the long-term value that comes with an open, modular and modern instruction set architecture. The presence of cores like the Codasip L31 are making it easier and easier for customers to make that transition so they can reap the benefits of RISC-V. Sensors, security IP/software, IoT middleware and cloud connectivity available within the Intel Pathfinder for RISC-V IDE all help to mitigate perceived risk by demonstrating end-to-end capabilities at the pre-silicon stage.
Well, the cool thing about RISC-V is that it is an open standard, and that brings so many possibilities. But that can also be a challenge! Endless possibilities make it harder to make a choice and the evolving ecosystem can be hard to navigate.
Intel has blazed a path with Intel Pathfinder for RISC-V by making a first selection of recommended vendors, and from that stamp of quality, companies can explore and evaluate what best fits their needs.
As a key RISC-V processor IP vendor, it was obvious for Codasip to be part of the Intel Pathfinder for RISC-V ecosystem. Our L31 core is quite versatile so we chose to make it available to the wider embedded community through the program. It is a low-power, general-purpose, embedded RISC-V core that balances performance and power consumption. From IoT devices to industrial and automotive control, or as a deeply embedded core in a larger system, it brings local processing capabilities into a compact area.
Vijay: The initial beneficiaries are end-user segments addressed by the Codasip L31 core. Over time we hope Intel Pathfinder for RISC-V will include support from a broader range of Codasip cores. By harnessing our combined capabilities, we see a tremendous opportunity to accelerate the transition to RISC-V, thereby establishing it as a third mainstream compute architecture after x86 and Arm.
Rupert: Companies of all sizes, really. From SMEs to start-ups and bigger players. We give everyone access to high-class silicon ready proof points to get started with their RISC-V journey in a standard and stable environment. If they wonder whether they should go with our L31 core, they can see their use case brought to life. With Intel Pathfinder for RISC-V, our core can be integrated with a growing set of complementary IPs, multiple operating systems, and toolchains for IoT and embedded applications.
Vijay: In addition to being open and modular, RISC-V is free and easily licensable. In less than 10 years since its inception, RISC-V has made remarkable progress, driven largely by a well-knit ecosystem that includes academia & research in addition to a breadth of commercial organizations. The opportunities are vast, and based on what we have seen to date, the RISC-V market will reward organizations that not only build competitive products, but also foster collaborative models within the ecosystem.
Rupert: The RISC-V community is growing rapidly and continuously gaining market traction. It is attracting everyone, from university researchers to major industry players. There have been new processors and new ISAs in the past. But what is different about RISC-V is the ecosystem, a critical factor in the success of a processor architecture. More and more players are joining, more and more software and tools are available, broadening the adoption of the ISA. This in turn is attracting more ecosystem partners in an accelerating virtuous spiral, and it is that spiral that is driving the success of RISC-V, in which Intel and Codasip play a major role for the embedded industry.
Vijay: By combining Codasip RISC-V IP with the Intel Pathfinder for RISC-V developer tools, we are making it easier for customers to go from product concept to a mature platform that includes silicon and software. Intel Pathfinder for RISC-V combines RISC-V IP with complementary security IP, accelerators for AI/ML, Vision and Audio processing, as well as sensor and middleware integration, thus providing an accelerated software development path for customers that reduces time to market, cost and complexity/risk.
Rupert: The program removes the barrier to the adoption of RISC-V by providing a level of standardization that can make RISC-V adoption easy with some level of consistency for the software developer community. By collecting vendors of different types, the program can kickstart the development of a new system by bringing together all the great capabilities already out there, including L31. You can instantly start an IoT application based on our L31 core, combine it with other IP, integrate security from Crypto Quantique, and verify it all using Siemens EDA even before committing to silicon.
Collaboration is key.
Those who collaborate are better set for success in RISC-V than those who don’t. Thanks to an ecosystem coming together, the risk of RISC-V is reduced, and you can easily explore options when you are ready to make the shift. Codasip and Intel are exploring further possibilities for collaboration, and you will see more offerings going forward, always with quality and ease of use in mind.
Give it a try!
* © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. No product or component can be absolutely secure.
July 18, 2022
I was fortunate enough to attend the 59th Design Automation Conference (DAC) in San Francisco last week. Aside from the Covid closure in 2020 I’ve been going to DAC since 1995. Many people, including me, arrived to the San Francisco with a bit of trepidation. After all, 58th DAC had low attendance and it was only ~7 months ago. What was the DAC 2022 conference going to be like? How would Covid affect things? Would international travelers come to San Francisco?
Frankly, I was impressed! Yes, the exhibit hall is smaller than it used to be. Yes, the attendance is not what it was in the 2000’s… and yes, there were times where it was quite slow on the exhibit floor. At the end of the day the many international travellers did show up and the conference and exhibits were quite well attended. At Codasip we met with customers and prospects from all over the world — Korea, Japan, Europe, the US, and more.
I started the week on Sunday at the well-attended Needham analyst event with Charles Shi. Charles mentioned there were concerns about a semiconductor down cycle but thought that the EDA and IP companies could push through without too much trouble. Charles expanded on his talk from December 2021 noting that Moore’s Law continues to slow and this is, at least partially, driving wafer and transistor costs higher as transistor density is no longer doubling in each new node.
I latched onto a comment that Charles made — that leading systems companies were designing their own chips. Companies like Apple, Tesla, and others were beating Moore’s Law and differentiating their product by building their own custom chips.
If scaling is no longer an option in most situations, optimization means customizing a processor for your specific application. The only way forward to differentiate is architectural innovation. If you haven’t already, I encourage you to look at our whitepaper on semiconductor scaling.
The demo at our booth showed what Jon Taylor, our Director of Application Engineering, presented at Embedded World 2022 on customizing RISC-V cores to accelerate neural networks. You can watch his talk here.
One of the highlights of my week was the executive dinner hosted by the Codasip management team. The intimate event included customers, partners, and industry supporters. We shared ideas, told stories, and had a lot of laughs together. There is nothing quite like having this time in person – the online meetings just can’t compare. One takeaway from that event was the optimism around the industry, RISC-V, and Codasip.
A couple of weeks ago, Embedded World 2022 showed us that the RISC-V genie is now out of the bottle. It was therefore no surprise to see that a key theme of this DAC was RISC-V. RISC-V appeared in papers, posters, presentations, tutorials, and in the exhibit hall. There were new university ideas, cool security projects, open-source and commercial implementations of RISC-V, and verification technologies, to name a few.
The question is no longer if RISC-V is too risky too adopt — but is it too risky not to adopt.
And companies are adopting RISC-V. The RISC-V International community is made up of over 200 companies from 50 countries. A quick search on Indeed.com shows over 400 job postings referencing RISC-V in the US alone. This doesn’t even include the dozens of jobs that Codasip has open!
One very interesting thing we heard at DAC is about John Deere designing their own ASICs to improve customer productivity and help to deliver more value to farmers. The company, by investing in building its internal capabilities around data science and analytics, is transforming into a data-driven technological manufacturing company. The John Deere Operations Center delivers value to farmers with tools and features that enable them to easily access farm information to better manage their daily operations. This article is a nice summary of how John Deere is leveraging AI, IoT and data analytics.
All in all, it was a great week at the Design Automation Conference. I’m certainly looking forward to the 60th DAC in 2023. It was great to see all of the new innovation in the industry and especially around RISC-V. RISC-V is here and the team as Codasip is proud to be leading the way with our unique approach to RISC-V.
July 7, 2022
With semiconductor scaling no longer being an option in most situations, optimization means customizing the processor for your specific application. With the right approach and right tools, processor design automation can enable innovation and differentiation. One way of achieving this is to create an application-specific processor by owning the design. To do this efficiently, manual efforts should be reduced to the minimum. Let’s see, in this blog post, how processor design automation can drive innovation and foster differentiation.
The semiconductor industry is facing scaling limitations (if you haven’t yet, read our white paper on semiconductor scaling) for new applications that require efficient execution of algorithms for data processing. For example, vision, voice and vibration applications. In this context, the only way forward to differentiate is architectural innovation.
The ideal baseline for differentiating is the RISC-V ISA. Free, open, and modular, it allows custom extensions to create a unique processor tailored for specific needs and applications. Most of the time, there is no need to create an entirely new product from scratch. Customizing an existing commercial RISC-V processor is the most efficient way to design a new product with optimal features and PPA.
This approach, which is getting more and more attention, brings new opportunities for software and hardware developers, with complete design freedom. These new opportunities also come with efforts that have not been experienced before. Indeed, any modification to the processor architecture must be reflected in both hardware and software, and be verified. To minimize efforts, make the best use of resources and reduce time to market, processor design automation is key.
Customization requires the right tools and needs to be considered from the beginning. Codasip RISC-V cores are all designed in CodAL, with customization in mind, so they can be modified seamlessly. Based on C, CodAL is an architecture description language very close to standard programming languages, easy to adopt for processor design automation. This ownership gives you design freedom while keeping control of costs and resources.
Design freedom can start with architecture exploration. Codasip Studio with CodAL generates a Software Development Kit that includes all the tools software programmers will need. Profiling benchmarks, getting performance statistics, making some changes in the design, and seeing the results in just a few minutes: this is all possible with Codasip Studio. But that’s not all.
Studio and CodAL generate everything needed to be ready for production. Indeed, customization is not just about modifying the RTL. It also includes generating all tools required to design a quality core that can be monetized. Codasip customization solutions take care of this. Customers modify the core as needed in CodAL, the rest is automated.
This unique description language allows the automated generation of the hardware and software tools that are required. With a single, unified toolchain, our customers automatically get the RTL, simulators, testbenches, the verification environment, and a customized compiler that understands their custom hardware and how to take advantage of it. They create a unique product with tools that simplify processor design and verification for all developers.
Processor design automation with Codasip solutions is something we will talk about extensively at DAC 2022 in July, the Design Automation Conference held in San Francisco, California. If you would like to know more about it, visit us at our booth or book a meeting with us.
June 28, 2022
The last Embedded World was back in February of 2020, but the event was hit hard by Covid-19 with many exhibitors and visitors deciding to pull out last minute. No-one knew then that it would take almost two and half years before the embedded industry would regroup again in Nuremberg. Even now, in June 2022, a lot of people are still hesitant to travel and the volume of visitors in the halls was half this time compared to the glory days of 2018 or 2019. However, compared to December 2021 and the RISC-V Summit in California, this time there were no empty aisles and there was a steady flow of visitors walking the halls. Embedded World 2022 was an important conference for us and the RISC-V community.
You know when you meet children that you have not seen in a few years and cannot get over how much they have grown? Well, probably some people had that same experience with RISC-V this time around at Embedded World 2022. Because it was evident that RISC-V is all grown up now!
Thinking back to my second week at Codasip in 2017, I was at our stand at Embedded World. We had displays that spoke of RISC-V and processor design automation, but our exhibit caused raised eyebrows. The typical passer-by simply said, “What is RISC-V?” or “who are you?”.
In contrast, by this year, everyone knows about RISC-V, students and large and small corporations alike. We were also a strong contributor of presentations to the RISC-V Pavilion too. And a good thing for us here at Codasip is that most people seem to also know us as a leading RISC-V IP provider.
Codasip is also no longer a well-kept secret, and we were well sought out by customers, partners and the media. Whether it’s our technology, or because of all the recruitment activities, it’s evident we’ve created a lot of interest. (And yes, we are still hiring, check out our open positions.)
If someone wasn’t sure what Codasip does, they most probably do after this week. Our customizable, low-power L31 embedded processor was awarded an Embedded World Best in Show by Embedded Computing Design magazine and the strong team on the Codasip stand was demonstrating our capabilities in delivering low-power embedded AI. In addition, we announced Apple macOS support in Codasip Studio, plus secure boot for Codasip processors, in collaboration with Veridify, and our friends at XtremeEDA and Crypto Quantique announced secure deployment using Codasip IP.
Well, one company in security software whose offering is partly based on standards driven by Arm said they were expanding into RISC-V, because their customers wanted easier migration from Arm to RISC-V. In contrast though, another security software company said that for them they were not yet ready to support RISC-V based on the limited number production RISC-V devices in the field. But given the interest in RISC-V that would change in time. The industry is definitely at a tipping point – the RISC-V genie is out of the bottle!
Also, we heard an opinion about RISC-V compiler quality being better than Arm, which is interesting indeed. There’s a long way to go, but with a rapidly growing ecosystem delivering a plethora of customizations and optimizations using the open RISC-V ISA, and with better tools on top of that, RISC-V is outstripping expectations and increasingly we think RISC-V is really starting to keep Arm and other established ISAs awake at night.
The next chance to meet the Codasip team is at DAC, at the Moscone Center in San Francisco on July 10-14 in booth #1451.
May 16, 2022
I was discussing with a colleague about the concept of architecture license in RISC-V. I realized that, in the open-source world, it can be a little tricky to grasp.
In a traditional processor IP model, there is a clear distinction between an off-the-shelf IP license that gives some level of configuration but no customization, and a fairly expensive architecture license enabling a licensee to use the instruction set with their own custom microarchitecture.
With RISC-V, the complication comes from the fact that it is often described as “an open-source architecture”, so people believe that some source code is licensed. But actually that is not the case at all.
In a traditional model, things are quite straight forward. A standard license for Arm or MIPS lets the customer use an RTL design but not change it at all (aside from a few configuration options perhaps).
Meanwhile, for customers willing to spend a lot of money, an architecture license gives them the right to modify how a processor executes instructions (the issue width, the cache size, etc.). However, it does not generally give the right to modify the instructions (with some exceptions such as the Cortex-M33 that supports Arm Custom Instructions, allowing the implementation of bespoke data processing operations, or Cadence Tensilica).
In an open-source model such as RISC-V, things are somewhat different
The RISC-V architecture is usually described as “open-source”, which implies everyone can use it at no cost.
However, a better description of RISC-V is that it is an “open architecture” or “open standard”. In that sense RISC-V is like C, Wi-Fi or LTE with RISC-V International performing the role of (respectively) ANSI, IEEE 802.11 and 3GPP in defining and managing standards that people are free to implement as they choose. But that is a written standard – not an implementation or a microarchitecture.
Just as is the case with those other open standards, RISC-V licenses can either be open-source or commercial.
You can download open-source designs and have complete freedom to modify them however you wish. Boom, PULP, SweRV and other open-source designs give absolute freedom. But that comes with a cost: they are not supported, the verification is often troublesome, and they may not be of sufficient quality to use in a commercial design. Some companies do use them accepting those compromises; others are understandably wary.
Or you can buy a commercial RISC-V design. There are many companies offering high quality cores delivered as RTL with warranty and full product support. These can be an excellent solution for many customers. Then we are back to something similar to the traditional model: a sort of black box design – although based on an open-standard ISA – in that it cannot be modified or customized to address specific needs. But for many purposes that generic product will be a good fit.
Codasip, as a RISC-V core vendor, does a lot of business on this basis: customers buy a standard RISC-V processor core delivered as RTL and SDK, with high performance, “best-in-class” verification and full support. That is without any architecture license fees, to use it as it is, off the shelf.
But Codasip offers another option. This is an architecture license – and more – delivered as a source code in the CodAL processor description language.
Many of our customers buy a standard Codasip processor IP product delivered as CodAL source and then use Codasip Studio™ which enables them to modify it freely. We provide the flexibility to modify both the microarchitecture and the ISA, precisely what one needs to Design for Differentiation. Customization at ISA level brings higher performance and optimization. What is more, the power and elegance of the Codasip Studio toolset makes this very easy.
This is different to, for example, an Arm architecture license in three ways:
Arm, even with an architecture license, constrains what you are allowed to do. Codasip does not: it is your core and you have control.
Arm cores are developed internally, in traditional ways and not designed to be easy to modify. In contrast, all of Codasip’s cores are developed using Studio and are designed expressly to make customization (both ISA and microarchitecture) straightforward and efficient. That includes automatically creating the software toolchain (customized compiler etc) and verification.
Traditionally the limitation of architecture licenses has been both the cash cost of the license and the engineering resources (cost) required to take advantage of it. Codasip and Studio now make that far easier and hence more affordable with a complete end-to-end architecture customization solution. This dramatically changes the cost equation both of the architecture license fee and the engineering resources required.
Codasip offers the best of both worlds: a portfolio of high-quality standard cores that are a good fit for standard applications, with full verification and support. Or you can upgrade to a cost-effective architecture license, freely customize the core in an easy-to-use environment and have a unique product for your unique needs.
May 5, 2022
The semiconductor industry has changed and nowhere is this more visible than in the automotive industry. Global chip shortages have highlighted how dependent we are on silicon to keep cars on the roads. These shortages are also keeping wait times for new vehicles at an all-time high.
Add to this an influx of non-traditional players into the market and it’s easy to see why the automotive sector is arguably the hottest in the tech world right now. A new marketplace in automotive innovation and technology is taking shape with a battleground between existing pillars, tech giants and new business models. The ability to differentiate in this market is the key to success, bringing subtly different needs and requiring solutions with a different approach.
Two things are fundamentally changing in the automotive industry: the concept of software-defined vehicles (SDVs) and the need for democratizing innovation at design level. This transition from hardware to software unlocks new services and solutions for car manufacturers, enabling the delivery of updates and upgrades over the air for a better driver experience. And here, computing is a focus for the next generations of vehicles.
Bringing hardware closer to the system engineering is a different approach and exactly what Codasip can enable. The combination of Codasip Studio technology with RISC-V processor IP delivers access to rapid innovation, ownership and cost reduction right into the hands of automotive players. These are companies of all sizes that are experiencing the pains today. Democratizing processor design is a real demand that is accelerating automotive innovation in the supply chain. Codasip and RISC-V offer the ability to innovate rapidly at design level by reducing cost and complexity.
The ability to differentiate in a rapidly evolving sector such as automotive is key to success, or even survival. Owning the ability to Design for Differentiation is crucial and that is exactly what Codasip enables.
Centered in Europe, we are surrounded by the world’s largest market for automotive innovation and manufacturing and away from geopolitical challenges. We are surrounded by leading experts and customers and are able to work closely with them to build a world-class capability by deeply understanding the challenges and find solutions. These solutions benefit our automotive customers and their end customers – as well as the wider automotive industry, to some extent.
Design for differentiation is our buzzword. We are unlocking the true potential of RISC-V by providing our customers with best-in-class quality IP and processor design automation technology with the potential to enable and accelerate the innovation that the automotive industry needs through processor customization. In a reshaping world and supply chain, we are enabling innovation at a much lower cost, removing the barrier to entry, leading into ownership of the processor design.
Having security and safety embedded by design and allowing our customers to rapidly make changes to the design while maintaining safety, security integrity and proof of the design – without a lengthy design cycle – is fundamental.
Despite chip shortages, chip innovation is booming and that applies especially to the automotive sector. It is abundantly clear that the future of automotive is through innovation and differentiation. Codasip’s processor design automation technology and EDA tooling has the potential to accelerate innovation in the automotive supply chain, and to enable innovation in electrification and safe and secure applications for connected and autonomous vehicles.
Jamie Broome recently joined Codasip as VP Automotive after more than 20 years at Imagination Technologies. Read the press release on his appointment and the exciting opportunities ahead for Codasip and the industry.
May 2, 2022
With closed processor Instruction Set Architectures (ISA) with limited access to processor Intellectual Property (Arm and x86), university professors have often limited their research to two main spheres: optimizing software algorithm(s) and external hardware. University researchers have not been able to consider optimizing the processor due to the lack of access to processor Intellectual Property (IP). Where these two spheres overlap, trade-offs are made to optimize the solution. A conventional research barrier is the exclusion of processor architecture optimization. Coprocessors or external accelerators can be explored, but they are limited and costly in solving tomorrow’s technological challenges in Processor Security, Functional Safety, Intelligent Memories, and Artificial Intelligence.
We launched the Codasip University Program in March 2022 to support you, engineering professors and students, and advance technology that will solve tomorrow’s technological challenges. Because of Moore’s Law and Dennard’s Scaling challenges, computer architects have developed solutions through integrating multiple homogenous and heterogenous cores. Tightly coupling application acceleration and application-specific requirements into the processor core is a new research domain to solve tomorrow’s computational needs. Let see, in this blog post, how you can jump start on this opportunity with our program.
Conventional research has been limited to software algorithms and external hardware resources due to fixed and closed processor architectures. Unfortunately, an important component of the research equation – the processor – has been left out.
Let’s start with an example. Sequential memory elements such as register files and pipeline registers are not commonly protected against single bit upsets that may occur via an alpha particle or a security attack. To protect from these upsets, external processor monitors or a 1 out of 2 voting strategy can be considered, but greatly increasing the design and validation complexity at increased cost.
Optimizing the processor architecture itself is missing from the above solutions. Three elements are now available to you through the Codasip University Program to break through this barrier and to include tightly coupling the application’s requirements into the processor.
With access to RISC-V cores and Codasip Studio, you, university researchers and students, can now explore new processor architectures that integrate application-specific features and acceleration – and ultimately become tomorrow’s solutions and engineers.
With RISC-V IP and Codasip Studio, resources can now be brought into the processor for optimization and solution trade-offs can occur between all three spheres.
Continuing our single bit upset example, can we solve this fault by integrating a solution into the processor to protect its memory and register bits?
Processor architecture optimization involves two key concepts: tightly coupling application-specific functionality into the processor and enhancing the processor performance through cycle-count reduction.
Using Codasip Studio and RISC-V cores, you can add Hamming encoding to write to the register file and decoding upon reads. The register file is now protected through two-bit error detection and single-bit error correction (ECC) by developing functions in the processor’s Cycle Accurate (CA) model using CodAL.
CodAL is an architectural high-level description language that describes the processor’s ISA (Instruction Accurate (IA) model) and the hardware implementation (Cycle Accurate (CA) models). Pipeline registers can be protected with parity to provide real-time bit error detection. When a fault is detected, the parity checker can assert a processor exception for handling. ECC and parity can be extended to either the L1 or L2 caches.
For a set of applications, would integrating the processor into solving single bit upsets reduce design complexity, development and validation time, as well as solution cost? Applications can be accelerated by reducing program clock cycles assuming the clock frequency remains constant. Using Codasip Studio’s profiler, you can analyze the most common sequence of operations to replace two or more RISC-V instructions with a single new instruction. Using CodAL to update both the IA and CA models, this new instruction becomes available to the application developer through Codasip Studio’s assembler and C-compiler.
Empowering processor architecture optimization enables you to imagine new avenues of research that was not feasible before. Here are just three possibilities…
Get started with the Codasip University Program to explore new processor architecture optimizations through integrating application-specific functionality and acceleration.
March 24, 2022
The semiconductor industry has changed hugely in the last 3 or 4 decades. Around 1980 some larger semiconductor companies were strongly vertically integrated, not only designed and manufactured their products, but even made their own processing equipment and in-house EDA tools. Today almost every semiconductor company uses 3rd party equipment for IC manufacturing and designs using 3rd party EDA tools and 3rd party IP. A key reason why the disaggregation of the semiconductor industry has happened is the use of open standards.
There is no universally agreed definition of an open standard but it is generally agreed that they are available on a reasonable and non-discriminatory basis. In many cases, especially in SoC design, such standards are available on a royalty-free basis. Many open standards are owned by independent bodies such as the IEEE, OSI and IETF (internet engineering task force) rather than by companies. In such cases the further development of the standard is through an open process with widely-based participation.
It is worth looking at open standards for SoCs from both hardware and software angles. For embedded software, C and C++ have been well-established as open standards. Middleware and real-time operating systems (RTOS) have therefore frequently been supplied as source code using one of these languages. Some porting may be necessary where there are processor- or peripheral-dependencies but generally design teams can tackle this.
In many current devices, especially in IoT, an SoC has either wired or wireless communications. Such links require communication protocols based on open standards such as Ethernet or Bluetooth LE. Such networked devices are also likely to require some sort of security and again open standards enable secure communications.
In digital hardware design, the microarchitecture is described in a hardware description language. Both Verilog and VHDL are IEEE open standards and the RTL description will be synthesized to the gate level. Processors and peripherals are frequently connected by AMBA buses which are a set of standards owned by Arm but available royalty free.
Verification will frequently be done using UVM (Universal Verification Methodology) which again is an open standard managed by the Accellera industry organisation. Power intent can be expressed in UPF (Unified Power Format) – another Accellera standard.
Finally, at the physical design level layout is required for silicon manufacturing. For decades GDSII, originally developed at Calma, has been used as the main interchange format. More recently, OASIS (Open Artwork System Interchange Standard) has been used as an open standard for layout.
Open standards have provided many benefits to industry. Firstly, they have provided interoperability between chips, between software packages and between design tools. This has enabled disaggregation.
Secondly, if there are open standards there is an opportunity for an ecosystem of products and vendors to develop. For example, with C there are a host of software development tools available as well as middleware and RTOS products for embedded software reuse. At the hardware level there is a wide range of EDA tools that use open standards such as Verilog, UVM and OASIS. This means that development teams have a wide choice of vendors and do not need to depend on a single vendor.
Thirdly, an open standard means that one level of specification is already accomplished allowing product companies to focus on differentiation through their implementation.
However, the ‘elephant in the room’ is that there has been an obvious gap in the open standards. The ISA represents the all-important interface between hardware and software, but this has historically been almost exclusively the preserve of proprietary ISAs.
With RISC-V there is for the first time a truly open standard for an ISA with real industry support. The ISA combines a very lightweight base integer instruction set with the flexibility of standard and custom extensions. The RISC-V ISA does not specify a microarchitecture so, for example, Codasip has developed RISC-V processor cores with three-, five- and seven-stage pipelines thus allowing designers to match a core to their needs. IP vendors differentiate with microarchitecture.
An immediate benefit for embedded software suppliers and for SoC developers is that it is attractive to offer middleware as binaries (as well as just source code). This alone should help RISC-V adoption to accelerate by simplifying work for embedded software developers.
Using an open ISA is a catalyst for a rapidly expanding ecosystem embracing processor IP vendors, software development tool providers, software companies and semiconductor companies. Just as in networking, token ring proprietary products were squeezed out by the growing ecosystem of Ethernet around 1990, we can expect proprietary ISAs to be squeezed out by RISC-V in the coming decade.
Lastly for companies developing their own processor cores, the base instruction set is available royalty free. The modularity and extendibility of the RISC-V ISA means that basic instructions are already defined, and the developers can focus on the specific value add of their core or accelerator.
Adopting RISC-V is now a low-risk choice for embedded SoC developers. The crucial gap in SoC open standards has been closed to the benefit of both hardware and software developers.
March 16, 2022
Keith Graham has been appointed to lead the new Codasip University Program. From helping tomorrow’s processor experts to developing the technologies that will solve tomorrow’s technical challenges, and accelerating innovation, we asked Keith what it is all about. Keith explains how the University Program will help today’s engineering students become the next generation of processor engineers our industry needs.
Becoming the Head of Codasip’s University Program is my dream job. The technological challenges of tomorrow are yet to be solved and the next generation of processor engineers will need innovative, best-in-class IP and technology to achieve this. Before joining Codasip, I was already convinced by the benefits of customizing RISC-V processors using Codasip’s unique technology. Having many years of experience developing courses for the University of Colorado, it felt obvious to me that Codasip and universities could do great things together.
Over my thirty-seven years upon graduating Penn State, I have been a hardware design engineer, worked in start-ups, sold semiconductors, a small business owner, and a senior instructor at the University of Colorado at Boulder. It is time for me to give back to the next generation.
In the 1980s, it was an era that it was not difficult to find a company that was developing a custom processor, but it ended due to the need to standardize software. The number of mainstream processors narrowed to around 6 in the 1990s. Now, with the open architecture of RISC-V, it solves the issue of standardized software with the advantage of enabling processor customization.
To solve tomorrow’s technology challenges in security, artificial intelligence, and many other domain specific applications, we need a new generation of processor engineers.
We are at the start of a new golden age of processor designs. Through the University Program, we will be making available innovative curriculum material, supporting research faculty, and creating an ecosystem to spur innovation and product development.
The Codasip University program helps universities develop the theory and the design skills that companies developing tomorrow’s SoCs will need. Together with our technology partners we provide engineering students and researchers with the support they need for their research projects.
Students and researchers will be provided with computer engineering curriculums, assignments, materials, and industry-grade tools.
By partnering with universities, we create a Design for Differentiation Ecosystem that will encourage sharing of knowledge, experiences, ideas and designs. Universities will have access to FAQs, knowledge boards, a design database to share solutions, and will be able to participate in community activities such as design contests.
It is essential to provide students with access to CodAL and Studio. This unique technology will enable them to focus on becoming innovative processor designers. CodAL, our patented architecture description language, is more efficient and less error prone compared to using a less abstracted language like Verilog. Perfect for students.
With Studio, we want to provide the ideal processor design automation platform that will help future SoC designers build their ideas into something that could become a commercial product.
Interested in the Codasip University Program? Learn more on our website and get in touch with us.