10 December, 2018
Campbell, California – December 10th 2018 – Codasip, the leading supplier of RISC-V® embedded processor IP, announced today that Mythic, a leader in artificial intelligence (AI) computing technology, has selected Codasip’s configurable Bk3 processor and Codasip Studio for future neural networking chips. Mythic, based in Redwood City, California, and Austin, Texas, will deliver powerful, life-enhancing AI solutions that customers can push into anything, from fitness bands and hearing aids to self-driving cars and security cameras. The solutions are developed on a unique approach to neural network processing. The Mythic Intelligence Processing Unit (IPU), which performs the inference step of deep neural networks inside the same flash memory array which stores the neural network’s weights, delivers huge advantages in performance, cost, and power consumption versus alternative solutions. “We chose Codasip’s Bk3 RISC-V processor and Codasip Studio for our PCIe-attached IPU deep learning accelerator because it gave us the flexibility to create a truly unique processor that was specific to our needs, while maintaining compliance to the RISC-V standard,” stated Ty Garibay, VP of Hardware Engineering at Mythic. “While we have the expertise to build our own RISC-V processor, we determined that Codasip Studio, with its automatic generation of both verified hardware and fully compatible software toolchain, was a more efficient approach and allowed us to focus on other critical areas of the product development.” The Codasip Bk3 processor, based on the RISC-V open instruction set architecture (ISA) definition, features a single 3-stage in-order execution processor pipeline and offers optional caches, IEEE 1149.1 debug, branch prediction, and industry standard bus interfaces. Further, the Bk3 – like all Codasip RISC-V implementations – is fully configurable and extensible, offering great advantage over traditional, fixed-configuration processor IP cores. With Codasip Studio, designers can begin with a high-level description of a RISC-V micro-architectural implementation defined and delivered by Codasip, and then describe their desired architectural and ISA modifications in the CodAL architecture description language, and then automatically synthesize the design’s RTL, testbench, virtual platform models and processor SDK (C/C++ compiler, debugger, profiler, and other parts). Time that would otherwise be required to maintain a complete SDK and implementation is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation. “We welcome Mythic to the growing roster of customers that are partnering with Codasip to deliver innovative products based on the RISC-V architecture,” stated Chris Jones, Codasip’s Vice President of Marketing. “RISC-V is ideal for machine learning applications, and Mythic will deliver revolutionary products that employ highly optimized Codasip RISC-V cores.”
