Codasip Demo – Accelerated DSP on a Customized RISC-V Core

The video shows Codasip L31 (3-stage 32-bit RISC-V) processor on FPGA that runs several DSP algorithms: FIR filtering, FFT, Viterbi decoding. The processor is customized with Codasip Studio and enhanced with hardware accelerators that improve the performance of these DSP algorithms.