Mid-range 32-bit RISC-V CPU for smart devices

Codasip L31 is a low-power, general-purpose, embedded RISC-V CPU providing an ideal balance between performance and power consumption. From IoT devices to industrial and automotive control, or as a deeply embedded core in a larger system, this versatile CPU brings local processing capabilities into a compact area. 

You can easily customize L31 with Codasip Studio to add your own instructions and boost the efficiency of your system.

Features and benefits

Configurable design

Codasip L31 core block diagram

L31 is a 32-bit RISC-V embedded CPU (RV32IMCB), featuring a hardware multiplier and divider. It can also include an additional FPU (RV32IMFCB) to accelerate floating-point operations for applications that require signal processing. 

L31 is highly configurable with optional features that can significantly boost its performance, including: 

  • Instruction and data caches 
  • Instruction and data tightly-coupled memories (TCM) 
  • Branch prediction  
  • Physical Memory Protection 

Software development

Using standard AMBA AHB or AXI Lite interfaces, L31 can easily be connected to existing systems and interconnects. What is more, L31 is designed to simplify software development, with essential features to support developers: 

  • Debug interface – using standard RISC-V Debug specification  
  • Instruction-accurate model – for fast execution of software, before hardware is available 
  • Cycle-accurate model – for software algorithm optimization, when time constraints require precise execution 
  • Full trace capability – in the cycle-accurate model, to hunt hard-to-find bugs 

Customizable RISC-V CPU

If you need a core specifically tailored for its task, you can modify the L31 core. Delivered in CodAL with an architecture license, the core is fully customizable with Codasip Studio at microarchitecture and ISA level. 

With Codasip unique tools and design methodology, the custom instructions that you add are understood by our compiler and debugger, and are included in the instruction-accurate and cycle-accurate models. Whether you require higher performance, lower power, or need to reduce area for a particular set of applications, you have the full freedom to modify the L31 core, and Codasip tools will generate the RTL and the SDK for you.

Certified configuration


Codasip L31AS is a 32-bit RISC-V embedded processor that is certified according to ISO 26262, ASIL B. It includes two instances of Codasip L31 in a dual-core lockstep configuration. 

Licensing the L31 core

Choose the L31 IP licensing model that fits your needs: 

  • A Codasip standard license contains all the benefits of a high-quality core, delivered in RTL, directly usable in your product. 
  • A Codasip enhanced architecture license includes the full CodAL high-level description language for L31, to allow you to fully customize it.
Off-the-shell RISC-V CPU Delivered as RTL Production ready
Customizable RISC-V CPU Delivered as Codal source code Modifiable with Codasip Studio

Use cases


  • Hardware Development Kit  
  • Software Development Kit – including instruction-accurate and cycle-accurate models 
  • FPGA bitstream 
  • Scripts and testbenches for front-end and back-end 
  • Enabling software 
  • Documentation

FPGA evaluation

Get an FPGA evaluation platform for L31, the perfect tool for you to evaluate the standard off-the-shelf core but also any customization you want to do. You can use it throughout the development of your custom product to check the functionality, develop and optimize software, but also for demos, product prototyping, and more.

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