Munich, Germany – November 3rd, 2020 – Codasip GmbH, the leading supplier of customizable RISC-V® embedded processor IP, announced today that NeuLinker, a high-profile Beijing-based company focused on cutting-edge custom computing technologies, has selected Codasip’s Bk5 RISC-V-based core and the Codasip Studio customization toolset for their security and AI-powering solutions.
Beijing NeuLinker Information Technology Co. Ltd. specializes in ASIC designs and system solutions for the domains of AI, IoT, and blockchain. Their mission is to provide the technology for custom, secure and shared computing as required today.
NeuLinker selected Codasip Bk5 for a project that aims to enable AI functionality on IoT devices and to accelerate security management and privacy protection of blockchain data. Bk5 not only meets the design requirements for the Digital Signature Algorithm (DSA) support; it also provides the benefits of energy efficiency and cost advantages for the deployment and further development of the related technology and its ecosystem.
“The Codasip Bk5 IP offered high performance and customizability, while the Codasip company provided mature development environment and good technical support,” said Mr. Liu, the Co-Founder and Chip Design Director at NeuLinker. “Overall, we were very pleased to get a complete, reliable, and easy-to-use solution for our design.”
Apart from Bk5, NeuLinker also licensed Codasip Studio, the complete automated CPU design EDA toolset that will enable them to easily customize the Bk5 IP and flexibly respond to changing priorities and updated product requirements.
“Our technology is unmatched in producing both rapid and reliable results at reduced cost,” said Karel Masařík, CEO of Codasip. “We are confident that by selecting the combination of Codasip Bk5 and Studio, NeuLinker got their future development needs covered, no matter how complex they are and how much they change over time.”
The Codasip Bk5 processor is based on the RISC-V open instruction set architecture (ISA). Bk5 features a single 5-stage in-order execution processor pipeline, optional caches, dynamic branch prediction, JTAG and RISC-V debug, and industry standard bus interfaces (AMBA). It also includes support for privilege-mode standard extension, memory protection unit and TCM, allowing it to easily run a variety of free and commercial RTOSs. The Bk5-64 variant with 64-bit address space and data support is ideal for modern data-intensive applications like storage, networking, AI, and IoT. Bk5 is fully configurable and extensible in compliance with the RISC-V standard.
With Codasip Studio, designers begin with a high-level description of a RISC-V micro-architectural implementation defined and delivered by Codasip. Then they describe the desired architectural and ISA modifications in the CodAL architecture description language. Finally, Studio automatically generates the design’s RTL, testbench, virtual platform models, and SDK (C/C++ compiler, debugger, profiler, and other parts). Time that would otherwise be required to maintain a complete SDK and HDK is significantly reduced thanks to the methodology that uses an Instruction Accurate (IA) processor model in CodAL for SDK generation and a Cycle Accurate model for implementation.
Featured image by courtesy of NeuLinker.