by Brett Cline
As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading to San Francisco with a bunch of other Codasippers some of the Codasip team was headed for the RISC-V Summit in Munich.
The event is nowhere on the scale that it used to be. In fact, the entire exhibit could probably now fill one floor of the Moscone. But the level of foot traffic remained high throughout the show and the team and I spoke to a fair number of people over the 3 days of exhibits. I was impressed with the number of fresh faces and new startups. There was something interesting to see in all corners of the tradeshow floor. And… incredibly the weather was, well, incredible.
It’s been clear for the last few years that the era of RISC-V is upon us. In fact, every person who visited us at least knew a little about it. The move away from Arm and the desire for design freedom is only growing stronger and the only sensible option is RISC-V. The inherent flexibility of RISC-V provides a platform and when that is combined with customization technology things really get interesting. To that end, we demonstrated our latest EDA product – Codasip Studio Fusion.
For years, Codasip Studio has been the go-to toolset for generating both processor RTL and the necessary software development tools from a single high-level model. The latest version, Codasip Studio Fusion, enhances this key capability and introduces multiple levels of processor customization depending upon your goals. It allows you to configure the core from predefined options or even create and/or modify the entire processor with absolute freedom. Studio Fusion will automatically generate the RTL, verification structures, and the software developer kit (SDK) including compiler, debugger, and profiler.
In Studio Fusion we’ve added a cool new capability that we call Custom Bounded Instructions, or CBI. With CBI the designer can customize the processor a be sure that they have not broken the verification. We do this through a set of rules, managed by Studio Fusion. Our demo on the floor (below) showed a design with over 40 customizations and no need to re-verify the core.
It wouldn’t be a tech show in 2024 without mention of AI
Yes, AI is everywhere right now. And yes, Codasip is no exception to this. At this year’s show we demonstrated an AI inference algorithm for anomaly detection executing on a customized embedded RISC-V core – all of which is running on an FPGA board. This demo highlights just how powerful the ability to easily customize your core is. With just a limited number of custom instructions we were able to dramatically increase the throughput, reduce the cycle count per inference, and massively reduce the power consumption (all while running at a quarter the clock frequency).
This latest demo features the newly announced Codasip L110 embedded core.
You can watch this demo here:
With great power comes great responsibility
One of my personal highlights of the show was attending my colleague Filip Benna’s talk. In this talk Filip outlines how to easily customize a RISC-V processor while keeping verification in mind. Now the benefits of customization are fairly obvious – with the scaling laws failing the options to improve performance are becoming more limited. But the verification burden of adding even a few custom instructions to a core can be a daunting task.
Well not anymore. As Filip outlined in his talk Codasip’s Bounded Customization framework ensures that new instructions do not impact the base core’s operation. Codasip Studio prevents design engineers from modifying the base core design files. With a pre-verified core, reverification of the register file, base execution units, pipeline, and similar components is unnecessary. To verify new instructions, Codasip Studio Fusion offers verification tools, including a Random Instruction Generator and an RTL plus Reference model via a Verification framework.
You can watch the full talk here:
A successful 61st DAC
With that DAC is over for another year and thoughts can move on to the next event. The team and I will be at the RISC-V Summit in October. We’d love to see to you there.
In the meantime, you can read up on last week’s RISC-V Summit in Munich (thanks to whoever scheduled it at the same time as DAC). And why not watch some more of the videos from the 61st DAC here.
Until next time.
Brett
