Scaling is failing is a drum we’re banging here at Codasip: the end of Moore’s Law, Dennard Scaling, Amdahl’s limits… Semiconductor process shifts are costing more but no longer providing the expected and required performance improvements.

Something must be done, and fortunately there is RISC-V with its open ISA that lets designers tune not only the microarchitecture, but the ISA itself, to co-develop hardware and software and provide truly optimized performance, power, and area. Codasip’s Studio™ EDA tool and CodAL processor description language are arguably the easiest and most proven way to make such customization.

Customers today are telling us that they want more “heterogeneous compute” and “domain specific acceleration”, a topic covered by our CMO Rupert Baines in a post about Apple’s recent M1 Pro launch.

And this is exactly the Design for Differentiation Codasip is providing for our customers. Our incredibly supportive existing and new investors are committed for the long-term to expand Studio, CodAL, and our portfolio of RISC-V cores to include the high-end and new functionality we will unveil in the coming quarters.

As we keep saying, Codasip has been a well-kept secret, but will not be for much longer. Indeed, our customers have already deployed an estimated 2 billion cores designed with Codasip tools!

If you want to hear more about #ScalingIsFailing, come along to my #RISCVSummit keynote on Wednesday, December 8th at 14:10 PST (that’s 2210 GMT/UTC), find out more on our RISC-V Summit 2021 page – hope to see you there, in person or virtually.