RISC-V Summit US 2023: CHERI in full bloom!

RISC-V Summit US 2023

RISC-V Summit US 2023 did not disappoint. With more than 1,000 attendees over 3 days, our team was full on. After announcing our 700 family and the first ever commercial implementation of CHERI a couple of weeks before the event, we were prepared for what was, we believe, the best RISC-V event we’ve ever attended. […]

Custom processor design just became easier

Codasip & SmartDV partnership blog interview

One-stop-shopping for cores and peripherals Codasip and SmartDV recently announced joining forces to simplify and accelerate custom processor design by offering our customers the possibility to license Codasip RISC-V IP and the necessary peripheral IP from SmartDV under a single contract. To better understand this promising collaboration, we asked Erik Panu, SmartDV, and Mike Eftimakis, […]

Shifting left for success: Highlights from the Siemens EDA User 2 User conference

Highlights from U2U Siemens EDA conference by Codasip: shift left

I was at the Siemens EDA User 2 User conference in Munich last week. This one-day event is the perfect opportunity to learn, grow and connect with technical experts who design innovative products using Siemens EDA tools in Europe. This year’s edition was obviously not disappointing in any way (OK, perhaps the weather could have been […]

5 reasons to attend RISC-V Summit Europe

RISC-V Summit Europe Barcelona 2023, blog featured image

The first-ever RISC-V Summit Europe will be held in Barcelona in June 2023! Enjoying the city at this time of the year is pretty amazing. The tapas, the beach, Las Ramblas, Gaudi’s architecture… We know. We will be there. As the European RISC-V leader. And here are 5 more reasons for you to be there […]

5 things I will remember from the 2022 RISC-V Summit

Codasip at 2022 RISC-V Summit

After an intense week at the 2022 RISC-V Summit in San Jose, California, and a long journey back to Munich (30 hours!) I am back at our Codasip headquarters, fueled with energy and positive thoughts. I obviously had plenty of time in transit to reflect on the event which, once again, was unique in many […]

Being a design verification engineer is fun and rewarding

light bulb on grey background

Philippe Luc, Director of Verification at Codasip, talked to students of the UK Electronics Skills Foundation (UKESF) about what it is like to be a verification engineer. On one hand the UKESF encourages young people to study electronics and pursue careers in this sector, and on the other hand Codasip is very keen to help […]

How to reduce the risk when making the shift to RISC-V

With the Intel® Pathfinder for RISC-V* program, Intel launched a development environment that enables companies of all sizes to start their RISC-V journey. Codasip makes its L31 RISC-V embedded core available to the embedded community through the program. We asked Vijay Krishnan, Intel Corporation, and Rupert Baines, CMO at Codasip, to tell us more about […]