The Codasip Group participates in multiple RISC-V research & development projects both as a standalone beneficiary and a consortium partner. These projects benefit from public funding/co-funding at national or international level.
Codasip High-end processor IP and high-level design tools for RISC-V
Project acronym: Codasip RISC-V Solution for High-end Processor IP
Project details available here.
Project funding: Codasip RISC-V Solution for High-end Processor IP has received funding under the European Innovation Council (EIC), Grant Agreement 190101116 (with Codasip Gmbh (Germany) and Codasip s.r.o. (Czech republic) as grant beneficiaries).
Project status: Active
Ultra-Energy Efficient And Secure Neuromorphic Sensing And Processing At The Endpoint (consortium project)
Project acronym: NimbleAI
Project details available here.
Project funding: NimbleAI has received funding from the EU’s Horizon Europe Research and Innovation programme (Grant Agreement 101070679), and by the UK Research and Innovation (UKRI) under the UK government’s Horizon Europe funding guarantee (Grant Agreement 10039070). Codasip s.r.o. (Czech republic) is one of the consortium partners of this project.
Project status: Active
Scaling extreme analYtics with Cross-architecture acceLeration based on OPen Standards (consortium project)
Project acronym: Syclops
Project details available here.
Project funding: This Horizon Europe Project “SYCLOPS” has received funding from the European Union HE Research and Innovation programme under grant agreement No 101092877. Codeplay Software, as a UK participant in this project is supported by UK Research and Innovation Scheme grant numbers 10048920. Codasip s.r.o. (Czech republic) is one of the consortium partners of this project.
Project status: Active
Together for RISC-V Technology and ApplicatioNs (consortium project)
Project acronym: TRISTAN
Project funding: This project “TRISTAN” has received funding from the European Union HE Research and Innovation programme under grant agreement No 101095947. Codasip Gmbh, as a German participant in this project, is supported by the Federal Ministry of Education and Research under grant no. 16MEE0275.
Project status: Active
Acoustic sensor solutions integrated with digital technologies as key enablers for emerging applications fostering society 5.0 (consortium project)
Project acronym: Listen2Future
Project details available here.
Project funding: The project “Listen2Future” has received funding from the European Union HE Research and Innovation programme (via CHIPS JU) under grant agreement No 101096884. Codasip Gmbh, as a German participant in this project, is supported by the Federal Ministry of Education and Research under grant no. 16MEE0244.
Project status: Active
High Performance, Safe, Secure, Open-Source Leveraged RISC-V Domain-Specific Ecosystems (consortium project)
Project acronym: ISOLDE
Project details available here.
Project funding: The project “ISOLDE” has received funding from the European Union HE Research and Innovation programme under grant agreement No 101112274. Codasip s.r.o, as a Czech participant in this project, is supported by the Ministry of Education, Youth and Sports.
Project status: Active
Open source deep learning platform dedicated to Embedded hardware and Europe (consortium project)
Project acronym: NEUROKIT2E
Project details available here.
Project funding: This project “NEUROKIT2E” has received funding from the European Union HE Research and Innovation programme (via CHIPS JU) under grant agreement No 101112268. Codasip Gmbh, as a German participant in this project, is supported by the Federal Ministry of Education and Research under grant no. 16MEE0298.
Project status: Active
Research and development of EDA tools and multi-core application processors with accelerators based on RISC-V architecture
Operational Program: Czech recovery plan
Priority axis: 1.5. Digital transformation of businesses
Activity: 1.5.1.4 IPCEI support in the field of Microelectronics and communication technologies, Call I.
Project registration number: 2320000004
Support recipient: Codasip s.r.o.
The project is focused on the creation of a new generation of software tools for the design of EDA (Electronic Design Automation) chips designed for the design of RISC-V processors and on the research and development of design technologies for high-performance multi-core application processors.
The aim of the project is to create a new ecosystem for RISC-V IP cores to support innovation across industries with technology based on open architecture, in mass production quality and of European origin.
THIS PROJECT IS FINANCIALLY SUPPORTED BY EU FUNDS THROUGH THE CZECH RECOVERY PLAN.
Project status: Active
Research and development of configurable embedded RISC V processors
Operational Program: The Operational Program Technologies and Application for Competitiveness
Call number and title: 01_22_002_ Application – Call I
Project registration number: CZ.01.01.01/01/22_002/0000818
Support recipient: Codasip s.r.o.
Project details: The project is focused on the research and development of a completely new design solution for the so-called built-in configurable RISC-V semiconductor processors.
The ambition of the project is to innovate the processor IP and design methodology processors through custom EDA tools new generation so that processors can be adapted to the solution distribution of semiconductor scaling.
Project funding: This project is co-financed by the European Union from the Regional Development Fund within the Operational Program Technologies and Application for Competitiveness under the authority of the Ministry of Industry and Trade.
Project status: Active
OPEN AND PROGRAMMABLE ACCELERATORS FOR DATA-INTENSIVE APPLICATIONS IN THE CLOUD (consortium project)
Project acronym: CHORYS
Program: Horizon Europe RIA
Call number and title: Digital and emerging technologies for competitiveness and fit for the Green Deal (HORIZON-CL4-2024-DIGITAL-EMERGING-01-CNECT)
Project registration number: 101189551
Support recipient: Codasip GmbH
Project details: The project prioritizes support for data-intensive applications in the context of the European Open Computing Architecture by developing and demonstrating open and programmable accelerators. Through the project, the goal is to demonstrate that European cloud providers and their customers can leverage open accelerators for near-data processing and asynchronous data services to improve the performance, energy-efficiency, and cost of data-intensive applications.
Project funding: This project is co-financed by the European Union from the European Health and Digital Executive Agency.
Project status: Active
RISC-V GENERATION OF HIGH PERFORMANCE AUTOMOTIVE PROCESSORS AND COMPUTING PLATFORMS
Project acronym: RIGOLETTO
Program: HORIZON JU Innovation Actions
Call number and title: Service Oriented Framework for the Software Defined Vehicle of the future (HORIZON-JU-Chips-2024-1-IA)
Project registration number: 101194371
Support recipient: Codasip GmbH, Codasip UK Ltd.
Project details: The Rigoletto project will establish the foundation for a next-generation Automotive Hardware Platform based on the open RISC-V instruction set architecture, bolstering and securing Europe’s leading role in the automotive electronics industry. The project aligns with the high-level goal of EU Chips Joint Undertaking and the of the industry-led Vehicle of the Future initiative: namely, the creation of a RISC-V based automotive hardware platform strongly linked with the formation of an open, software-defined vehicle ecosystem led by European automotive manufacturers and suppliers. Rigoletto aims at developing RISC-V intellectual property components, including processor cores, accelerators, interconnects, memory hierarchy and peripheral subsystems. A wide range of performance profiles will be targeted for next-generation DCUs and ZCUs, to enable increasingly electrified, automated, and connected vehicles.
Project funding: The project received funding from the European Union HORIZON JU Innovation Actions programme (via CHIPS JU) under grant agreement No 101194371. Codasip GmbH, as a German participant in this project, is supported by the Federal Ministry of Research, Technology and Space under grant no. 16MEE054.
Project status: Active
Digital Autonomy for RISC-V in Europe (Specific Grant Agreement 1)
Project acronym: DARE SGA 1
Program: Horizon Europe (HORIZON)
Call number and title: Specific Grant Agreement for the development of European Processor and Accelerators based on RISC-V (HORIZON-EUROHPC-JU-2024-DARE-SGA-04)
Project registration number: 101202459
Support recipient: Codasip GmbH, Codasip s.r.o.
Project details: HPC Digital Autonomy with RISC-V in EurHPC Digital Autonomy with RISC-V in Europe (DARE) will address Europe’s deficit in digital autonomy for High Performance Computing and AI, by creating truly European products for European supercomputers for research and industry. The project builds upon the solid research foundation from EPI, EUPILOT, EUPEX, DEEP-SEA, eProcessor, MEEP and related projects, and it takes advantage of the open RISC-V ecosystem, chiplet revolution and open-source software. It is the first phase of the ambitious 6-year plan set out in the DARE FPA proposal, and it defines clear intra- and inter-phase SMART KPIs and success criteria, on the road to European digital autonomy while supporting current and future computing needs. We will develop and tape-out, in advanced technology, three RISC-V-based chiplets: a vector accelerator for high-precision HPC and emerging applications, an AI Processing Unit inference accelerator for HPC AI applications and an HPC-focused European general-purpose processor. These chiplets bring cost and yield advantages by going beyond the reticle size limitations imposed by monolithic chips and they will be integrated in a mix-and-match fashion to build specific systems. DARE uses a carefully selected set of the most significant European HPC and AI applications to drive hardware and software activities in a HW/SW co-design scheme, in order to ensure that the project’s HW and SW results meet the requirements of the European HPC and AI communities. It will build a complete SW stack, optimized for DARE HW, that supports these cutting-edge applications. To make rapid progress, SW and HW developments proceed in parallel, leveraging early access to RISC-V hardware emulation and simulation. Finally, the project will elaborate a detailed technical roadmap and pathfinding, defining the major steps and milestones to be followed in the next phase, in order to achieve the goal of nextgeneration post-exascale EU supercomputers.
Project funding: The DARE SGA1 project has received funding from the European High-Performance Computing Joint Undertaking (JU) under grant agreement No 101202459. The JU receives support from the European Union’s Horizon Europe research and innovation programme and Spain, Germany, Czechia, Italy, Netherlands, Belgium, Finland, Greece, Croatia, Portugal, Poland, Sweden, France and Austria. Funded by the European Union.
Project status: Active
Fully Optimized Root of Trust for Robust Embedded Secure Systems
Project acronym: FORTRESS
Program: Horizon Europe (HORIZON)
Call number and title: Approaches and tools for security in software and hardware development and assessment (HORIZON-CL3-2024-CS-01)
Project registration number: 101225722
Support recipient: Codasip s.r.o.
Project details: The foundation of modern cybersecurity lies in the secure boot process, ensuring only trusted and authenticated software runs on a device. By validating code integrity through cryptographic signatures, secure boot upholds the Confidentiality, Integrity, and Availability triad, acting as the first line of defense against tampering, malware, and unauthorized changes. Currently, secure boot relies on traditional cryptographic algorithms like RSA. However, the advent of quantum computing threatens these systems, as quantum algorithms like Shor’s could break them, necessitating a transition to Post-Quantum Cryptography. The European Union and relevant agencies, such as ANSSI and BSI, advocate for a Post-Quantum/Traditional (PQ/T) hybrid cryptographic model, combining quantum-resistant algorithms with traditional cryptography for added resilience. Implementing quantum-safe secure boot remains challenging due to the performance, scalability, and compliance trade-offs of PQ/T solutions. However, to date there seems no significant progress has been made in this domain. FORTRESS aims to address these challenges by developing a scalable and efficient hybrid secure boot architecture. It will design a flexible Root of Trust, integrating both traditional and post-quantum algorithms while exploring trade-offs between security, performance, and cost. The project will focus on hardware-software co-design principles, enabling diverse platforms – embedded systems, edge devices, and Critical National Infrastructure – to transition to quantum-resistant architectures seamlessly. Additionally, the project will engage industry stakeholders to align with regulatory and standardization efforts, ensuring practical deployment and maximum impact. By developing a critical building block for a wide range of applications, FORTRESS will safeguard Europe’s digital infrastructure, fostering resilience and leadership in the post-quantum era.
Project funding: The FORTRESS project (grant registration number 101225722) is funded by the European Union under the Horizon Europe research and innovation programme.
Project status: Active
Implementation of a Flexible and Diverse Work Culture at Codasip s.r.o
Project registration number: CZ.03.01.02/00/22_012/0003837
Applicant: FLECTO, s.r.o.
Project partner: Codasip s.r.o.
Project details: The main goal of the project is to introduce a work culture that is responsive to the needs of employees, enabling them to reconcile their work and personal lives at the employer Codasip s.r.o. through the implementation of measures in the field of flexibility, and the creation of suitable conditions to achieve a diverse and effectively functioning collective.
Project implementation period: 1/11/2023 – 31/10/2025 (24 months)
Key Activities:
KA 1 – Processing of analyzes of the initial state
KA 2 – Creation of strategies
KA 3 – Implementation in the field of flexibility and diversity
KA 4 – Final evaluation of strategies
Project funding: The project is co-financed by the European Union as part of the Operational Program Employment Plus.
Project status: Active
RISC-V Digital Architecture for the Next Generation of Connected Era
Project acronym: Codasip
Project funding: Codasip has received funding under the European Innovation Council (EIC), Grant Agreement 881172 (with Codasip Gmbh (Germany) and Codasip s.r.o. (Czech republic) as grant beneficiaries).
Project status: Successfully closed
Hardware platform for high-demand computing with a RISC-V processor in the Internet of Things
Call number and name: 01_16_076 ICT and shared services – creation of new IS/ICT solutions – II. call
Project details: The project deals with the development of advanced processors based on the RISC-V standard. These processors will be intended for a new generation of portable and stationary devices, which will already fulfill the essence of the upcoming era of the Internet of Things with their design and functions.The main activity of the project is the development of a prototype of advanced processors. The output of the project is a hardware platform prototype using FPGA technology.
Project funding: This project is co-financed by the European Union from the regional development fund within the Operating program of business and innovation for competitiveness under the authority of the Ministry of Industry and Trade under the project registration number CZ.01.4.04/0.0/0.0/16_076/0009460 with Codasip s.r.o. (Czech republic) as grant beneficiary.
Project status: Successfully closed
