Configurable LLDB for (not only) embedded RISC-V processors

LLDB blog featured image

At some point, software developers or processor developers need to check and debug their code. They can do this at different levels, for example looking at waves or parsing printouts, but the preference is to check code in an interactive session. The debugger facilitates the interactive session by accepting developers’ commands, executing them, and showing […]

How the SYCLOPS project democratizes AI acceleration

Codasip Labs is all about innovation, and specifically the commercialization of that innovation. Naturally, with the rise of Artificial Intelligence (AI) and Machine Learning (ML), these areas have become a key focus for us. At the beginning of 2023, we joined the New Horizon Europe Project SYCLOPS (Scaling extreme analYtics with Cross-architecture acceLeration based on […]

Re-targetable LLVM C/C++ compiler for RISC-V

Featured image for blog Re-targetable LLVM C/C++ compiler for risc-v

RISC-V is a modular instruction set architecture (ISA) with great customization capabilities that enable innovation and differentiation without fragmentation. On top of the baseline modules from ratified/standard ISA extensions, such as integer instructions or floating-point instructions, designers can add custom instructions: pure design freedom! And the reasons for adding instructions are many: better performance, smaller […]

Making the most of the 60th DAC

Featured image for DAC 2023 blog

I just returned from a week in San Francisco where I attended the 60th Design Automation Conference. It was a typical week at DAC — cold weather in July, catching up with long-time industry friends, and lack of sleep from long days. Maybe I’m just cynical from having been to DAC since 1995 — which […]

Increasing design skills for custom compute

Blog image Codasip Design skills for custom compute

As discussed in an another blog post by Mike Eftimakis, there are limitations to traditional design methods that use “off-the-shelf” processor cores. Traditionally, software engineers try to fit their code to the constraints of the chosen processor hardware. The alternative is to co-optimize the hardware and software together to create a custom compute solution. You […]

Developing a customized RISC-V core for MEMS sensors 

Listen2Future project logo

We recently described how Codasip Labs is working with the NimbleAI project to push the boundaries of neuromorphic vision. Let’s talk about another cool project. This project is focused on another sense, hearing. We will use our unique Codasip Studio design toolset to develop a customized RISC-V core for MEMS (micro-electro-mechanical system) sensors. Again, technology […]

No one-size-fits-all approach to RISC-V processor optimization

Cover image blog Mike Eftimakis on No one size fits all approach to processor optimization

As the demand for high-performance processors continues to grow and semiconductor scaling laws continue to show their limits, the need for processor optimization is inevitable. As I explained in a previous blog, RISC-V is designed to enable this. However, there is no one-size-fits-all approach to processor optimization. As each workload and each application will have […]

design automation to drive innovation and differentiation

With semiconductor scaling no longer being an option in most situations, optimization means customizing the processor for your specific application. With the right approach and right tools, processor design automation can enable innovation and differentiation. One way of achieving this is to create an application-specific processor by owning the design. To do this efficiently, manual […]