Codasip and Metrics Design Automation Announce the Integration of the Metrics Cloud Simulation Platform in Codasip’s RISC-V SweRV Core™ Support Package Pro
August 5, 2020
August 5, 2020
Munich, Germany and Ottawa, Canada – August 5th 2020 – Codasip, the leading supplier of customizable RISC-V embedded processor IP, and Metrics Design Automation, providers of the only True Cloud EDA solution, today jointly announced the integration of the Metrics SystemVerilog RTL Simulation Platform within Codasip’s SweRV Core™ Support Package, the Professional version. This integration provides a very easy-to-use and inexpensive way for ASIC designers to verify modifications and enhancements they make to the SweRV embedded processor IP.
One of the major benefits of the open source RISC-V ISA is that it allows users to customize their processor IP for optimal implementation in domain-specific applications. With this valuable benefit however comes the responsibility to verify any changes made to the processor IP for functional accuracy. Codasip and Metrics have teamed together to address this requirement by making RTL verification available in the Cloud directly from the Codasip SweRV Core Support Package. SweRV and the Support Package users thus do not have to install and license any EDA software, do not have to make any expensive purchases of RTL simulation software, and have all the SweRV and verification IP required all preloaded in a Cloud cluster for immediate use.
“Codasip continues to expand its ecosystem for RISC-V embedded processor IP for the benefit of our customers,” says Karel Masařík, CEO of Codasip. “This integration of the Metrics Cloud Simulator in our SweRV Core Support Package is an example of making RTL verification easier and more affordable for Codasip customers and SweRV users.”
The Metric Cloud Simulator is a fully compliant SystemVerilog simulator and is the only RTL simulator available with a SaaS business model—users simply pay for use as a service. The implementation of Metrics simulator in the Cloud provides massive scalability so regression tests can run in parallel to complete in hours, not days.
“The popularity of RISC-V and in particular the SweRV open source processor IP has been impressive,” noted Doug Letcher, CEO of Metrics. “We are excited to partner with a leading RISC-V embedded processor IP vendor such as Codasip to deliver better usability, accelerated verification, and much more affordability of RTL simulation tools to the ASIC and SoC design community.”