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Tiny, 32-bit RISC-V core

The Codasip L11 core is our smallest RISC-V core and an extremely efficient implementation of the Codasip Series 1. It is ideal for low-power applications where silicon area matters in a broad range of devices. 

Features and benefits

Designed for differentiation

RISC-V core designed in CodAL, fully customizable with an architecture license.

Area player

Tiny 32-bit core ideal in simple, cost-sensitive devices.

16 registers

Implementing the RV32EMC ISA, L11 saves area by having 16 registers

Customizable RISC-V application core

If you require optimal PPA or need a core specifically tailored for its task, you can modify the L11 core. Delivered in CodAL with an architecture license, the core is fully customizable with Codasip Studio at microarchitecture and ISA level. 

Use cases

Small IoT devices



  • Hardware Development Kit  
  • Software Development Kit – including instruction-accurate and cycle-accurate models 
  • FPGA bitstream 
  • Scripts and testbenches for front-end and back-end 
  • Enabling software 
  • Documentation 

FPGA evaluation

Get an FPGA evaluation platform for L11, the perfect tool for you to evaluate the standard off-the-shelf core but also any customization you want to do. You can use it throughout the development of your custom product to check the functionality, develop and optimize software, but also for demos, product prototyping, and more.  

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