L11 is the smallest Codasip RISC-V core. This extremely efficient 3-stage pipeline implementation is ideal for low-power applications where silicon area matters in a broad range of devices.

Features and benefits

Configurable design

Diagram - L11 Core

L11 is a 32-bit RISC-V embedded CPU (RV32EMC), featuring a hardware multiplier and divider. It is configurable with optional physical memory protection to help boost its performance.

Software development

Using standard AMBA AHB or AXI Lite interfaces, L11 can easily be connected to existing systems and interconnects. What is more, L11 is designed to simplify software development, with essential features to support developers: 

  • Debug interface – using standard RISC-V
  • Debug specification  
  • Instruction-accurate model – for fast execution of software, before hardware is available
  • Cycle-accurate model – for software algorithm optimization, when time constraints require precise execution
  • Full trace capability – in the cycle-accurate model, to hunt hard-to-find bugs

Customizable RISC-V embedded core

If you require optimal PPA or need a core specifically tailored for its task, you can modify the L11 core. Delivered in CodAL with an architecture license, the core is fully customizable with Codasip Studio at microarchitecture and ISA level.

Use cases


  • Hardware Development Kit  
  • Software Development Kit – including instruction-accurate and cycle-accurate models 
  • FPGA bitstream 
  • Scripts and testbenches for front-end and back-end 
  • Enabling software 
  • Documentation 

FPGA evaluation

Get an FPGA evaluation platform for L11, the perfect tool for you to evaluate the standard off-the-shelf core but also any customization you want to do. You can use it throughout the development of your custom product to check the functionality, develop and optimize software, but also for demos, product prototyping, and more. 

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