DeepSeek’s aftermath: Lessons to learn as the dust settles
The Chinese AI company DeepSeek took the technology industry, and Wall Street, by storm with its language model achieving a reported 10x higher efficiency than AI industry leaders. You have seen the news and might be getting sick of the endless articles tagging onto it, but I would like to offer a different perspective. DeepSeek claimed […]
Cosmic Compute at the RISC-V Summit North America Hackathon
We had the pleasure of sponsoring and hosting a hackathon at the RISC-V Summit North America 2024 in Santa Clara, California. As part of our commitment to advancing CPU design, we invited participants to take on a challenging technical mission that tested their skill through Codasip Studio, our advanced design tool. This tool, along with […]
Announcing the launch of CHERI Alliance: A unified front against digital threats
By Ron Black In an era where cyber threats are becoming increasingly sophisticated, the formation of a new alliance dedicated to cybersecurity is not just timely but essential. Today marks the formal launch of CHERI Alliance, which brings together industry leaders—including Google, the University of Cambridge, the UKs National Cyber Security Centre (NCSC) and Codasip—united […]
NEUROKIT2E: A deep learning platform dedicated to embedded HW and Europe
by Giovanni Grandi Codasip participates in multiple RISC-V research & development projects co financed by the EU. This blog post will do a deep dive into one of these projects: NEUROKIT2E. This German consortium comprises a total of 25 partners around Europe. The project has received funding from the European Union HE Research and Innovation […]
Solving the RISC-V puzzle – optimal performance with zero risk
by Tora Fridholm This blog post summarizes a keynote presentation by our CEO Ron Black at the RISC-V Summit Europe 2024. You can watch a recording of the keynote presentation on RISC-V International’s YouTube channel. “RISC-V is inevitable” – This is a phrase often used by Calista Redmond, CEO of RISC-V International. Recent research by […]
3 steps to shrinking your code size, your costs, and your power consumption
Tariq Kurd, Distinguished Engineer and Lead IP Architect RISC-V is a powerful instruction set that is constantly evolving. One of the recent evolutions relates to code size reduction. Last year, the RISC-V Zc extensions were ratified. The team at Codasip led this work, and as I have been closely involved, I would like to explain […]
DAC 2024 – Showcasing the future of RISC-V through EDA
by Brett Cline As I sat on the plane in Boston it’s fair to say that I was curious about what DAC 2024 would bring. The previous year was much better than I expected but a cold June in San Francisco wasn’t exactly what I was dreaming about. Afterall, while I was heading to San […]
Sunny skies and electric energy: RISC-V Summit Europe 2024 shines in Munich
by Tora Fridholm This week, the 2024 edition of RISC-V Summit Europe took place in lovely Munich, Germany. Those of us who attended last year’s edition in Barcelona might not have expected the same weather but Munich was up for the challenge and served us a sunny, hot week, only interrupted by a thunderstorm that […]
Defining the software/hardware interface: A new paradigm enabled by Codasip Studio Fusion
by Keith Graham Before there was a mainstream open standard Instruction Set Architecture (ISA) like RISC-V, a computer processor’s software/hardware interface was generally defined by processor architects. The decisions of the instructions set, multi-issue, out-of-order, speculation, branch prediction or multi-core were to accelerate general purpose or a class, such as Digital Signal Processing (DSP), of […]