RISC-V (pronounced “risk-five”) stands for ‘reduced instruction set computer (RISC) five’. The number five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981.
The RISC concept (like the parallel MIPS development in Stanford University) was motivated by the fact that most processor instructions were not used by most computer programs. Thus, unnecessary decoding logic was being used in processor designs, consuming unnecessary power and silicon area. The alternative was to simplify the instruction set and to invest more in register resources.
The RISC I project implemented a mere 31, 32-bit instructions but 78 registers. It introduced the notion of register windowing which was a technique that was later adopted by the SPARC architecture. This was closely followed by the RISC II project which had an even larger register file (138 registers). RISC II also introduced 16-bit instructions which improved code density. The terms RISC III and RISC IV have been used to refer to the SOAR and SPUR projects in 1984 and 1988, respectively.
The RISC-V project was partly motivated by the fact that proprietary, closed ISAs were restricted by patents and license agreements. Krste Asanović of the University of California, Berkeley was convinced that there were great advantages in having a free, open ISA that could be applied to both academic and industrial projects. David Patterson, who had worked on earlier RISC projects, was also involved. In 2010, a 3-month project led to the development of a new instruction set, leading to the publication of the first RISC-V ISA specification in 2011.
In order to manage contributions from other parties, the RISC-V Foundation – now RISC-V International – was formed in 2015 as an open collaborative community, and the original developers of the ISA transferred their rights around RISC-V to this organisation. Since then, RISC-V International has managed further development of the RISC-V ISA.