Closing the Gap in SoC Open Standards with RISC-V
March 24, 2022
March 24, 2022
The semiconductor industry has changed hugely in the last 3 or 4 decades. Around 1980 some larger semiconductor companies were strongly vertically integrated, not only designed and manufactured their products, but even made their own processing equipment and in-house EDA tools. Today almost every semiconductor company uses 3rd party equipment for IC manufacturing and designs using 3rd party EDA tools and 3rd party IP. A key reason why the disaggregation of the semiconductor industry has happened is the use of open standards.
There is no universally agreed definition of an open standard but it is generally agreed that they are available on a reasonable and non-discriminatory basis. In many cases, especially in SoC design, such standards are available on a royalty-free basis. Many open standards are owned by independent bodies such as the IEEE, OSI and IETF (internet engineering task force) rather than by companies. In such cases the further development of the standard is through an open process with widely-based participation.
It is worth looking at open standards for SoCs from both hardware and software angles. For embedded software, C and C++ have been well-established as open standards. Middleware and real-time operating systems (RTOS) have therefore frequently been supplied as source code using one of these languages. Some porting may be necessary where there are processor- or peripheral-dependencies but generally design teams can tackle this.
In many current devices, especially in IoT, an SoC has either wired or wireless communications. Such links require communication protocols based on open standards such as Ethernet or Bluetooth LE. Such networked devices are also likely to require some sort of security and again open standards enable secure communications.
In digital hardware design, the microarchitecture is described in a hardware description language. Both Verilog and VHDL are IEEE open standards and the RTL description will be synthesized to the gate level. Processors and peripherals are frequently connected by AMBA buses which are a set of standards owned by Arm but available royalty free.
Verification will frequently be done using UVM (Universal Verification Methodology) which again is an open standard managed by the Accellera industry organisation. Power intent can be expressed in UPF (Unified Power Format) – another Accellera standard.
Finally, at the physical design level layout is required for silicon manufacturing. For decades GDSII, originally developed at Calma, has been used as the main interchange format. More recently, OASIS (Open Artwork System Interchange Standard) has been used as an open standard for layout.
Open standards have provided many benefits to industry. Firstly, they have provided interoperability between chips, between software packages and between design tools. This has enabled disaggregation.
Secondly, if there are open standards there is an opportunity for an ecosystem of products and vendors to develop. For example, with C there are a host of software development tools available as well as middleware and RTOS products for embedded software reuse. At the hardware level there is a wide range of EDA tools that use open standards such as Verilog, UVM and OASIS. This means that development teams have a wide choice of vendors and do not need to depend on a single vendor.
Thirdly, an open standard means that one level of specification is already accomplished allowing product companies to focus on differentiation through their implementation.
However, the ‘elephant in the room’ is that there has been an obvious gap in the open standards. The ISA represents the all-important interface between hardware and software, but this has historically been almost exclusively the preserve of proprietary ISAs.
With RISC-V there is for the first time a truly open standard for an ISA with real industry support. The ISA combines a very lightweight base integer instruction set with the flexibility of standard and custom extensions. The RISC-V ISA does not specify a microarchitecture so, for example, Codasip has developed RISC-V processor cores with three-, five- and seven-stage pipelines thus allowing designers to match a core to their needs. IP vendors differentiate with microarchitecture.
An immediate benefit for embedded software suppliers and for SoC developers is that it is attractive to offer middleware as binaries (as well as just source code). This alone should help RISC-V adoption to accelerate by simplifying work for embedded software developers.
Using an open ISA is a catalyst for a rapidly expanding ecosystem embracing processor IP vendors, software development tool providers, software companies and semiconductor companies. Just as in networking, token ring proprietary products were squeezed out by the growing ecosystem of Ethernet around 1990, we can expect proprietary ISAs to be squeezed out by RISC-V in the coming decade.
Lastly for companies developing their own processor cores, the base instruction set is available royalty free. The modularity and extendibility of the RISC-V ISA means that basic instructions are already defined, and the developers can focus on the specific value add of their core or accelerator.
Adopting RISC-V is now a low-risk choice for embedded SoC developers. The crucial gap in SoC open standards has been closed to the benefit of both hardware and software developers.