The RISC-V ISA contains mandatory base instructions and optional modules for floating point operations, vector processing, etc. The ISA itself can be further optimized with unique custom instructions that allow innovation and differentiation without fragmenting the ecosystem. This poster covers a re-targetable C/C++ LLVM compiler for RISC-V that can be generated for any combination of the optional modules and user custom instructions. The ISA description is provided as input in a C-based architecture description language called CodAL. The generator extracts textual and binary forms of instructions, their semantics, and other important information. With this, it generates the LLVM compiler including optimization passes that reflect the implementation of the instructions, the compiler backend, the library with intrinsic for complex instructions, and more.