Capability Hardware Enhanced RISC Instructions
As defined by the University of Cambridge, CHERI extends conventional hardware Instruction-Set Architectures (ISAs) with new architectural features to enable fine-grained memory protection and highly scalable software compartmentalization.
Increasing processor securitywith Custom Compute
*CVE stands for Common Vulnerability and Exposure as defined and explained here.
Award-winning commercial implementation of CHERI technology
Codasip X730 is the first commercially licensable CHERI implementation. It is based on our 64-bit high-performance A730 application core. Thanks to our unique Custom Compute methodology, we have extended the core with CHERI-based custom instructions, providing built-in, fine-grained memory protection.
Fine-grained memory protection
- 100% coverage in checking for memory errors using fine-grained memory protection against software attacks and programming errors
- Built-in CPU logic to check read/write permissions and validity of all memory accesses
- Unalterable hardware capabilities protect against known and future vulnerabilities
Simplicity of development
- Built-in unbreakable memory safety with CHERI technology
- Small increase in area and low impact on performance
- Increased security and cost saving simply through recompiling software with CHERI-aware compiler
- Ability to recompile only critical areas of code to reduce software effort to gain CHERI protection
- Fully backward compatible with standard RISC-V code
Codasip Prime CHERI-RISC-V exploration platform
Based on commercially available IP, Codasip Prime enables advanced development of memory-safe and secure software. The platform allows hardware and software engineers to evaluate and demonstrate the capabilities of CHERI technology, develop and run CHERI software, and integrate CHERI hardware into wider test systems.
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