Read CEO Ron Black’s ‘An open letter regarding Cyber Resilience of the UK’s Critical National Infrastructure’


Architecture optimization for university researchers

With closed processor Instruction Set Architectures (ISA) with limited access to processor Intellectual Property (Arm and x86), university professors have often limited their research to two main spheres: optimizing software algorithm(s) and external hardware. University researchers have not been able to consider optimizing the processor due to the lack of access to processor Intellectual Property (IP).   Where these two spheres overlap, trade-offs are made to optimize the solution. A conventional research barrier is the exclusion of processor architecture optimization. Coprocessors or external accelerators can be explored, but they are limited and costly in solving tomorrow’s technological challenges in Processor Security, Functional Safety, Intelligent Memories, and Artificial Intelligence.

We launched the Codasip University Program in March 2022 to support you, engineering professors and students, and advance technology that will solve tomorrow’s technological challenges. Because of Moore’s Law and Dennard’s Scaling challenges, computer architects have developed solutions through integrating multiple homogenous and heterogenous cores. Tightly coupling application acceleration and application-specific requirements into the processor core is a new research domain to solve tomorrow’s computational needs. Let see, in this blog post, how you can jump start on this opportunity with our program.

University research is often limited to hardware and software optimization

Conventional research has been limited to software algorithms and external hardware resources due to fixed and closed processor architectures. Unfortunately, an important component of the research equation – the processor – has been left out.

Let’s start with an example. Sequential memory elements such as register files and pipeline registers are not commonly protected against single bit upsets that may occur via an alpha particle or a security attack. To protect from these upsets, external processor monitors or a 1 out of 2 voting strategy can be considered, but greatly increasing the design and validation complexity at increased cost.

Optimizing the processor architecture itself is missing from the above solutions. Three elements are now available to you through the Codasip University Program to break through this barrier and to include tightly coupling the application’s requirements into the processor.

With access to RISC-V cores and Codasip Studio, you, university researchers and students, can now explore new processor architectures that integrate application-specific features and acceleration – and ultimately become tomorrow’s solutions and engineers.

Breaking through the research barrier to include processor architecture optimization

With RISC-V IP and Codasip Studio, resources can now be brought into the processor for optimization and solution trade-offs can occur between all three spheres.

Continuing our single bit upset example, can we solve this fault by integrating a solution into the processor to protect its memory and register bits?

Architectural optimization through application-specific integration into the core

Processor architecture optimization involves two key concepts:  tightly coupling application-specific functionality into the processor and enhancing the processor performance through cycle-count reduction.

Using Codasip Studio and RISC-V cores, you can add Hamming encoding to write to the register file and decoding upon reads. The register file is now protected through two-bit error detection and single-bit error correction (ECC) by developing functions in the processor’s Cycle Accurate (CA) model using CodAL.

CodAL is an architectural high-level description language that describes the processor’s ISA (Instruction Accurate (IA) model) and the hardware implementation (Cycle Accurate (CA) models). Pipeline registers can be protected with parity to provide real-time bit error detection. When a fault is detected, the parity checker can assert a processor exception for handling. ECC and parity can be extended to either the L1 or L2 caches.

For a set of applications, would integrating the processor into solving single bit upsets reduce design complexity, development and validation time, as well as solution cost? Applications can be accelerated by reducing program clock cycles assuming the clock frequency remains constant. Using Codasip Studio’s profiler, you can analyze the most common sequence of operations to replace two or more RISC-V instructions with a single new instruction. Using CodAL to update both the IA and CA models, this new instruction becomes available to the application developer through Codasip Studio’s assembler and C-compiler.

Explore new research avenues with the Codasip University Program

Empowering processor architecture optimization enables you to imagine new avenues of research that was not feasible before. Here are just three possibilities…

Get started with the Codasip University Program to explore new processor architecture optimizations through integrating application-specific functionality and acceleration.


Other blog posts