Does RISC-V mean Open Source Processors?
Blog by Roddy Urquhart, August 8, 2017.
“RISC-V means open-source processors.” This is a statement that I have often heard this year – however, is it true or false? The answer is in this blog post.
Do open standards automatically mean open source?
Before answering the question “Does RISC-V Mean Open-Source Processors?”, let's consider the broader issue of whether open standards automatically mean open source.
Open standards are widespread in technology. The communication protocols TCP/IP have been an open standard for decades. In wireless communication, Wi-Fi and Bluetooth are open standards with multiple versions.
In IC design, Verilog is an open standard maintained by the IEEE, and a widely used hardware description language. Verilog is used by a variety of commercial and open-source simulators. Incisive, Questa, and VCS are examples of well-known commercial simulators supporting Verilog, however Verilator & Cver are examples of open-source Verilog simulators. Generally, the commercial Verilog simulators are recognized for their high quality and performance.
RISC-V based processors can be either open-source or commercial
An open standard certainly does not rule out commercial products that use the standard. In the case of RISC-V, only the Instruction Set Architecture is standardized, leaving the microarchitecture and implementation to the processor developer. This gives ample opportunities for commercial processor cores. Commercial processor IP cores based on RISC-V will have their own features and value-add for example in microarchitecture and implementation.
Although there are open-source RISC-V processor cores including Zscale, Rocket, and BOOM from the University of California Berkeley, there are also commercial processor cores, such as Codasip RISC-V based processors.
What's New in Codasip

06/28/22
Blog
by Roddy Urquhart
Embedded World 2022 – the RISC-V genie is out of the bottle

06/22/22
Press Release
by David Marsden
Codasip adds Veridify secure boot to RISC-V processors

06/21/22
Codasip Studio
by David Marsden
Codasip Studio Mac extends potential to design for differentiation with RISC-V

06/21/22
Press Release
by David Marsden
Codasip L31 customizable RISC-V core is an Embedded World Best in Show

06/14/22
Press Release
by David Marsden
Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem

05/23/22
Blog
by Keith Graham
Single unified toolchain empowering processor research

05/16/22
Blog
by Rupert Baines
Design for differentiation: architecture licenses in RISC‑V

05/10/22
Press Release
by David Marsden
Codasip appoints SH Lee to deliver RISC-V innovations to Korean OEMs

05/05/22
Blog
by Jamie Broome
Building the highway to automotive innovation

05/03/22
Press Release
by David Marsden
Codasip adopts Siemens’ OneSpin tools for formal verification

05/02/22
Blog
by Keith Graham
Processor architecture optimization is not a barrier for university researchers

04/29/22
Blog
by Philippe Luc
Building a Swiss cheese model approach for processor verification