“So, RISC-V is an Open ISA, that means a RISC-V processor core is Open Source”.
This is a statement that I have often heard this year – however, is it true or false?
Before answering this, let’s consider the broader issue of whether open standards automatically mean open source. Open standards are widespread in technology. The communication protocols TCP/IP have been an open standard for decades. In wireless communication, Wi-Fi and Bluetooth are open standards with multiple versions. In IC design, Verilog is an open standard maintained by the IEEE, and a widely used hardware description language. Verilog is used by a variety of commercial and open source simulators. Incisive, Questa, and VCS are examples of well-known commercial simulators supporting Verilog, however Cver is an example of an open source Verilog simulator. Generally, the commercial Verilog simulators are recognized for their high quality and performance.
An open standard certainly does not rule out commercial products that use the standard. In the case of RISC-V, only the Instruction Set Architecture is standardized, leaving the microarchitecture and implementation to the processor developer. This gives ample opportunities for commercial processor cores. Commercial processor IP cores based on RISC-V will have their own features and value-add for example in microarchitecture and implementation.
Although there is a number of open source RISC-V processor cores including Zscale, Rocket, and BOOM from the University of California Berkeley, there are also commercial processor cores, for example the Codix-Bk3 and Codix-Bk5 from Codasip, among others.
Roddy Urquhart
